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freescale semiconductor data sheet: technical data document number: mpc5606s rev. 8, 11/2011 ? freescale semiconductor, inc., 2008?2011. all rights reserved. mpc5606s lqfp176 (24 x 24 mm) lqfp144 (20 x 20 mm) mpc5606s microcontroller data sheet ? single issue, 32-bit power architecture book e compliant cpu core complex (e200z0h) ? compatible with classic powerpc instruction set ? includes variable length encoding (vle) instruction set for smaller code size footprint; with the encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction over conventional book e compliant code ? on-chip ecc flash memory with flash controller ? up to 1 mb primary flash?two 512 kb modules with prefetch buffer and 128-bit data access port ? 64 kb data flash?separate 4 ? 16 kb flash block for eeprom emulation with prefetch buffer and 128-bit data access port ? up to 48 kb on-chip ecc sram with sram controller ? up to 160 kb on-chip non-ecc graphics sram with sram controller ? memory protection unit (mpu) with up to 12 region descriptors and 32-byte region granularity to provide basic memory access permission ? interrupt controller (intc) with up to 127 peripheral interrupt sources and eight software interrupts ? 2 frequency-modulated ph ase-locked loops (fmplls) ? primary fmpll provides a 64 mhz system clock ? auxiliary fmpll is available for use as an alternate, modulated or non-modulated clock source to emios modules and as alternate clock to the dcu for pixel clock generation ? crossbar switch architecture enables concurrent access of peripherals, flash memory, or ram from multiple bus masters (amba 2.0 v6 ahb) ? 16-channel enhanced direct memory access controller (edma) with multiple transfer request sources using a dma channel multiplexer ? boot assist module (bam) supports internal flash programming via a serial link (flexcan or linflex) ? display control unit to drive tft lcd displays ? includes processing of up to four planes that can be blended together ? offers a direct unbuffered hardware bit-blitter of up to 16 software-configurable dynamic layers in order to drastically minimize graphi c memory requirements and provide fast animations ? programmable display resolutions are available up to wvga ? parallel data interface (p di) for digita l video input ? lcd segment driver module with two software programmable configurations: ? up to 40 frontplane drivers and 4 backplane drivers ? up to 38 frontplane drivers and 6 backplane drivers ? stepper motor controller (smc) module with high-current drivers for up to six instrument cluster gauges driven in full dual h-bridge configuration including full diagnostics for short circuit detection ? stepper motor return-to-zero and stall detection module ? sound generation and playback utilizing pwm channels and edma; supports monotonic and polyphonic sound ? 24 emios channels providing up to 16 pwm and 24 input capture / output compare channels ? 10-bit analog-to-digital converter (adc) ? maximum conversion time of 1 ? s ? up to 16 internal channels, e xpandable to 23 via external multiplexing ? up to 2 deserial serial peripheral interface (dspi) modules for full-duplex, synchronous communications with external devices (extendable to include up to 8 multiplexed external channels) ? quadspi serial flash memory controller supporting single, dual, and quad modes of operat ion to interface to external serial flash memory; quadspi can be configured to function as another dspi module (mpc5606s only) ? 2 local interconnect ne twork flexible (linflex) controller modules capable of autonomous message handling (master), autonomous header handling (slave
mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 2 mode), and uart support; compliant with lin protocol rev 2.1 ? 2 full can 2.0b controllers with 64 configurable buffers each; bit rate programma ble up to 1 mbit/s ? up to 4 inter-integrated circuit (i 2 c) internal bus controllers with master/slave bus interface ? up to 133 configurable general purpose pins supporting input and output operations ? real time counter (rtc) with multiple clock sources: ? 128 khz slow internal rc oscillator or 16 mhz fast internal rc oscillator supporting autonomous wakeup with 1 ms resolution with maximum timeout of 2 seconds ? 32 khz slow external crystal oscillator, supporting wakeup with 1 s resolution and maximum timeout of one hour ? 4?16 mhz fast external crystal oscillator ? system timers: ? 4-channel 32-bit system timer module (stm)?included in processor platform ? 4-channel 32-bit periodic interrupt timer (pit) module ? software watchdog timer (swt) ? system integration unit (siu) module to manage resets, external interrupts, gpio, and pad control ? system status and configuration module (sscm) to provide information for identification of the device, last boot mode, or debug status, and provides an entry point for the censorship password mechanism ? clock generation module (mc_cgm) to generate system clock sources and provide a unified register interface, enabling access to all clock sources ? clock monitor unit (cmu) to monitor the integrity of the main crystal oscillator and the pll and act as a frequency meter, measuring the frequency of one clock source and comparing it to a reference clock ? mode entry module (mc_me) to control the device power mode, in other words, run, halt, stop, or standby control mode transition sequences, and manage the power control, voltage regulator, clock generation, and clock management modules ? reset generation module (mc_rgm) to manage reset assertion and release to th e device at initial startup ? nexus development inte rface (ndi) per ieee-isto 5001-2003 class two plus standard ? device/board boundary-scan testing supported per joint test action group (jtag) of ieee (ieee 1149.1) ? on-chip voltage regulator controller for regulating the 3.3 or 5 v supply voltage down to 1.2 v for core logic (requires external ballast transistor) ? the mpc5606s microcontrollers are offered in the following packages: 1 ? 144 lqfp, 0.5 mm pitch, 20 mm ? 20 mm outline ? 176 lqfp, 0.5 mm pitch, 24 mm ? 24 mm outline ? 208 mapbga, 1.0 mm pitch, 17 mm ? 17 mm outline (not a production package; available in limited quantities for tool development only) 1. see the device comparison table or orderable parts summary for package offerings for each device in the family.
mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 3 table of contents 1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 document overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.3 device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.4 mpc5606s series blocks . . . . . . . . . . . . . . . . . . . . . . . .5 1.5 details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2 pinout and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . .23 2.1 144 lqfp package pinouts . . . . . . . . . . . . . . . . . . . . .23 2.2 176 lqfp package pinout . . . . . . . . . . . . . . . . . . . . . .27 2.3 208 mapbga package ballmap . . . . . . . . . . . . . . . . . .28 2.4 pad configuration during reset phases . . . . . . . . . . . . .29 2.5 voltage supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.6 pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.7 system pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.8 debug pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 2.9 port pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3.2 parameter classification . . . . . . . . . . . . . . . . . . . . . . . .55 3.3 nvusro register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3.4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .56 3.5 thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .61 3.6 electromagnetic compatibility (emc) characteristics . .63 3.7 power management electrical characteristics. . . . . . . .65 3.8 i/o pad electrical characteristics . . . . . . . . . . . . . . . . . 74 3.9 ssd specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.10 reset electrical characteristics . . . . . . . . . . . . . . . . . 83 3.11 fast external crystal osci llator (4?16 mhz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 3.12 slow external crystal os cillator (32 khz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.13 fmpll electrical characteristics . . . . . . . . . . . . . . . . . 90 3.14 fast internal rc osci llator (16 mhz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.15 slow internal rc osci llator (128 khz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.16 flash memory electrical charac teristics . . . . . . . . . . . 92 3.17 adc electrical characteristics . . . . . . . . . . . . . . . . . . . 93 3.18 lcd driver electrical characteristics . . . . . . . . . . . . . 100 3.19 pad ac specifications . . . . . . . . . . . . . . . . . . . . . . . . 100 3.20 ac timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.1 144 lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.2 176 lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
mpc5606s microcontroller data sheet, rev. 8 overview freescale semiconductor 4 1 overview 1.1 document overview this document describes the device features and highlights impor tant electrical and physical ch aracteristics. for functional characteristics, see the mpc5606s microcontroller reference manual. 1.2 description the mpc5606s family of chips is designed to enable the development of automotive instrument cluster applications by providing a single-chip solution capable of hosting real-time appl ications and driving a tft display directly using an on-chip color tft display controller. mpc5606s chips incorporate a cost-efficient host processor core compliant with the power architecture ? embedded category. the processor is 100% user-mode compat ible with the power architecture and cap italizes on the available development infrastructure of current power architectur e devices with full support from available software driv ers, operating systems and configuration code to assist with users' implementations. offering high performance processing at speeds up to 64 mhz, the mpc5606s family is optimized for low power consumption and supports a range of on-chip sram and internal flash me mory sizes. the version with 1 mb of flash memory (mpc5606s) features 160 kb of on-chip graphics sram. see table 1 for specific memory and feature se ts of the product family members. 1.3 device comparison table 1. mpc5606s family device comparison feature mpc5602s mpc5604s mpc5606s cpu e200z0h execution speed static ? 64 mhz flash memory (ecc) 256 kb 512 kb 1 mb eeprom emulation block (ecc) 4 16 kb ram (ecc) 24 kb 48 kb 48 kb graphics ram no no 160 kb mpu 12 entry edma 16 channels display control unit (dcu) no no yes parallel data interface no no yes stepper motor controller (smc) 6 motors stepper stall detect (ssd) yes sound generation logic (sgl) yes lcd driver 40 4, 38 6 1 32 khz slow external crystal oscillator ye s
overview mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 5 1.4 mpc5606s series blocks 1.4.1 block diagram figure 1 shows a high-level block diagram of the mpc5606s series. real-time counter and autonomous periodic interrupt ye s ye s ye s periodic interrupt timer (pit) 4 ch, 32-bit software watchdog timer (swt) yes system timer module (stm) 4 ch, 32-bit timed i/o 2 8 ch, 16-bit ic/oc 16 ch, 16-bit opwm/ic/oc 3 adc 4 16 channels, 10-bit can (64 mailboxes) 1 flexcan 2 flexcan 2 flexcan can sampler yes sci 2 linflex spi 2 dspi 2 dspi 3 5 dspi quadspi serial flash interface no no yes i 2 c224 gpio 105 105 105 (144-pin package) 133 (176-pin package) debug nexus 1 nexus 1 nexus 2+ 6 package 144 lqfp 144 lqfp 144 lqfp 7 176 lqfp 208 mapbga 8 1 configuration is software-programmable. 2 ic-input capture, oc-output compare, opwm-output pulse width modulation. 3 this functionality is split over two emios blocks. 4 support for external multiplexer enabling up to 23 channels. 5 quadspi serial flash controller can be optionally used as a third dspi. 6 nexus2+ available on 176 lqfp as alte rnate pin function and on 208 mapbga. 7 not all features are available simult aneously in 144 lqfp package option. 8 the 208-pin package is not a production package; it is avai lable in limited quantities for tool development only. table 1. mpc5606s family device comparison (continued) feature mpc5602s mpc5604s mpc5606s
mpc5606s microcontroller data sheet, rev. 8 overview freescale semiconductor 6 figure 1. mpc5606s series block diagram six gauge drivers with stepper stall detect (ssd) 16 + 8 ch. 2 dspi test controller nexus 2+ nexus siu reset control interrupt external imux gpio & jtag crossbar switch pad control jtag port nexus port e200z0h external blocks 32-bit controller 2 flexcan 4 x 4 peripheral bridge peripheral interrupts from interrupt request external interrupts i/o instructions data voltage regulator nmi swt stm nmi siu . . . . . . . . . . . . (intc) 4 i 2 c . . . 2 linflex 2 x emios 16 ch. adc mpu (memory protection unit) clock monitor unit (cmu) controller flash flash power control mode entry clock generation module reset generation module unit module bam rtc/ sscm api 10-bit . . . dma dcu rgb tft output parallel data (pdi) interface sirc firc sxosc fxosc xtal/ extal xtal32/ extal32 16 mhz 128 khz 4?16 mhz 32 khz 4 pit lcd fp and bp signals sound generation speaker/ buzzer data and clock quadspi controller sram sram 2 fmpll port controller video controller sram sram 40 4 lcd logic
overview mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 7 1.5 details 1.5.1 low-power operation mpc5606s devices are designed for optimized low-power operation and dynamic power management of the core processor and peripherals. power management features include software-contr olled clock gating of peripherals and multiple power domains to minimize leakage in low-power modes. there are two static low-powe r modes, standby and stop, and six dynamic power modes?five run modes and halt. both low-power modes use clock gating to halt the clock for all or part of the device. standby mode also uses power gating to automatically turn off the power supply to parts of the device to minimize leakage. standby mode turns off the power to the majority of the chip to offer the lowest power consump tion mode. the contents of the cores, on-chip peripheral registers, and pot entially some of the volatile memory are lost. standby mode is configurable to make certain features available, with the disadvantage that these consume additional current: ? it is possible to retain the contents of the full ram or only 8 kb. ? it is possible to enable the internal 16 mhz or 128 khz rc os cillator, the external 4?16 mhz oscillator, or the external 32 khz oscillator. ? it is possible to keep the lcd module active. the device can be awakened from standby mode from any of as many as 19 i/o pins, from a reset, or from a periodic wakeup using a low-power oscillator. stop mode maintains power to the entire device, thus allowing th e retention of all on-chip registers and memory, and providing a faster recovery low-power mode than th e lowest standby mode. there is no need to reconfigure the device before executing code. the clocks to the core and peripherals are halted and can be optionally stopped to the oscillator or pll at the expense o f a slower startup time. stop mode is entered from run mode only. wakeup from stop mode is triggered by an external event or by the internal periodic wakeup, if enabled. run modes are the primary operating mode s where the entire device can be powe red and clocked. in run modes most processing activity is done. one default (drun) and four dynami c run modes are supported?run0...3. the ability to configure and select different run modes enables diff erent clocks and power configurations to be supporte d with respect to each other, and to allow switching between different operating conditio ns. the necessary peripherals, clock sources, clock speed, and system clock prescalers can be inde pendently configured fo r each of the four ru n modes of the device. halt mode is a reduced activity, low-power mode intended for mode rate periods of lower processing activity. in this mode the core system clocks are stopped but user-sel ected peripheral tasks can continue to run. it can be configured to provide more efficient power management features (switch-off pll, flash memo ry, main regulator, etc.) at the cost of longer wakeup latency. the system returns to a run mode as so on as an event or interrupt is pending.
mpc5606s microcontroller data sheet, rev. 8 overview freescale semiconductor 8 table 2 summarizes the operating modes of mpc5606s devices. table 2. operating mode summary 1 1 ta bl e ke y : on?powered and clocked op?optionally configurable to be enabled or disabled (clock gated) cg?clock gated, powered but clock stopped off?powered off and clock gated fp?vreg full performance mode lp?vreg low-power mode, reduced output capability of vreg but lower power consumption var?variable duration, based on the requir ed reconfiguration and execution clock speed bam?boot assist module software and hardware used for device startup and configuration operating modes: run halt stop standby por soc features core on cg cg off off ? peripherals op op cg off 2 2 the lcd can optionally be kept running while the device is in standby mode. off ? flash memory op op cg off off ? sram on on cg cg 3 3 all of the ram content is retained, but not accessible in standby mode. 8kb 4 4 8 kb of the ram content is retained, but not accessible in standby mode. ? graphics ram on on cg off off ? clock sources main pll op op cg off off ? auxiliary pll op op cg off off ? 16mhz irc on onopopop ? fxosc opopopopop ? 128khz irc ononononon ? 32 khz xosc op op op op op ? periodic wakeup ? opopopop ? wakeup input ? op op op op ? vreg mode fp fp lp lp lp ? wakeup times 5 vreg startup ? ? 50 ? s 250 s 250 s 250 s 6 irc wakeup ? ? 4s 4s 8s 8s flash memory recovery ? ? 20 s 100 s 100 s 100 s osc stabilization ? ? 1 ms 1 ms 1 ms 1 ms pll lock ? ? 200 s 200 s 200 s 200 s s/w reconfig ? ? ? var var ? mode switch over ? 200.69 s 24 s 28 s 28 s bam
overview mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 9 additional notes on low-power operation: ? fast wakeup using the on-chip 16 mhz internal rc oscillator allows rapid execution from ram on exit from low-power modes ? the 16 mhz internal rc oscillator supports low-speed code execution and clocking of periph erals when it is selected as the system clock and can also be used as the pll inpu t clock source to provide fast startup, without external oscillator delay ? mpc5606s devices include an internal voltage re gulator that includes the following features: ? regulates input to generate all internal supplies ? manages power gating ? low-power regulators support operation when in st op and standby modes to minimize power consumption ? startup on-chip regulators in <50 ? s for rapid exit of stop and standby modes ? low-voltage detection on main supply and 1.2 v regulated supplies 1.5.2 e200z0h core processor the e200z0h processor is similar to other processors in the e200zx series, but supports only the vle instruction set and does not include the signal processing extension for dsp applications or a floating point unit. the e200z0h has all the feat ures of the e200z0 plus: ? branch acceleration using br anch target buffer (btb) ? supports independent instruction and data accesses to diff erent memory subsystems, such as sram and flash memory via independent instruction and data bius the e200z0h processor uses a four stage in -order pipeline for in struction execution. 1. the instruction fetch (stage 1) 2. instruction decode/register file read /effective address calculation (stage 2) 3. execute/memory access (stage 3) 4. register writeback (stage 4) these stages operate in an overlapped fashion, allowing single clock instruction execution for most instructions. the integer execution unit consists of: ? 32-bit arithmetic unit (au) ? logic unit (lu) ? 32-bit barrel shifter (shifter) ? mask-insertion unit (miu) ? condition register manipulation unit (cru) ? count-leading-zeros unit (clz) ? 8 32 hardware multiplier array ? result feed-forward hardware ? hardware divider 5 a high level summary of some key durations that need to be considered when recovering from low-power modes. this does not account for all durations at wakeup. other delays will be necessary to consider, including but not limited to the external supply startup time. irc wakeup time must not be added to the overall wak eup time as it starts in parallel with the vreg. all other wakeup times must be added to determine the total startup time. 6 this is the startup of the regulator that happens after th e 5 v has reached beyond its por range. if the external supply ramp rate is slow, measure from when vreg has crossed beyond the por thres hold; otherwise, this value will depend on the ramp rate of the external supply (vddr).
mpc5606s microcontroller data sheet, rev. 8 overview freescale semiconductor 10 most arithmetic and logical opera tions are executed in a single cycle with the ex ception of the divide and multiply instruction s. a count-leading-zeros unit operates in a single clock cycle. th e instruction unit contains a pc incrementer and a dedicated branch address adder to minimize delays during change of flow operations. branch target prefetching from the btb is performed to accelerate certain taken branches . sequential prefetching is performed to ensure a supply of instructions into the execution pipeline. prefetched in structions are placed into an instruction buffer capable of holding four instructions. conditional branches not taken execute in a single clock. bran ches with successful target pr efetching have an effective execution time of one clock on e200z0h. all other taken branches have an execution time of two clocks. memory load and store operations are provided for byte, halfword, and word (32-bit) data with automatic zero or sign extension of byte and halfword load data as well as optional byte reversal of data. these instructions can be pipelined to allow effectiv e single-cycle throughput. load and store multiple word instructions allow low overhead context save and restore operations. the load/store unit contains a dedicated eff ective address adder to allow effective address generation to be optimized. also, a load-to-use dependency does not incu r any pipeline bubbles for most cases. the condition register unit supports the condition register (cr) and condition register operations defined by the power architecture. the condition register consists of eight 4-bit fields that reflect the results of certain operations, such a s: ? move ? integer and floating-point compare ? arithmetic ? logical instructions and provide a mechanism for testing and branching. vectored and autovectored interrupts are su pported. hardware-vectored interrupt suppor t is provided to allow multiple interrupt sources to have unique interrupt handle rs invoked with no software overhead. the cpu includes support for variable length encoding (vle) instruction enhancements. this allows the power architecture instruction set to be represented by a modified instruction se t made up from a mixture of 16-bit and 32-bit instructions. this results in a significantly smaller code size fo otprint without affecti ng performance noticeably. the cpu core is enhanced by an additional interrupt source, the non-maskable interrupt (nmi). this interrupt source is routed directly from package pins, via edge detection logic in the si u to the cpu, bypassing the interrupt controller completely. once the edge detection logic is programmed, it cannot be disabled, ex cept by reset. the nmi is, as the name suggests, completely un-maskable and when asserted will always result in the imme diate execution of the respective interrupt service routine. the nmi is not guaranteed to be recoverable. the cpu core has an additional wait for interrupt instruction that is used in conjunction with low-power stop mode. when low-power stop mode is selected, this instruction is executed to allow the system clock to be stopped. an external interrupt source or the system wakeup timer is used to restart the system clock and allow the cp u to service the interrupt. additional features include: ? load/store unit ? 1-cycle load latency ? misaligned access support ? no load-to-use pipeline bubbles ? thirty-two 32-bit general purpose registers (gprs) ? separate instruction bus and load /store bus harvard architecture ? reservation instructions for impl ementing read-modif y-write constructs ? multi-cycle divide (divw) and load multiple (lmw) store mult iple (smw) multiple class instructions; can be interrupted to prevent increases in interrupt latency ? extensive system development support through nexus debug port
overview mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 11 1.5.3 crossbar switch (xbar) the xbar multi-port crossbar switch suppor ts simultaneous connections between four master ports and four slave ports. the crossbar supports a 32-bit address bus width and a 32-bit data bus width. the crossbar allows four concurre nt transactions to occur from any master port to any slave port, but one of those transfers mu st be an instruction fetch from internal flas h. if a slave port is simultaneously reque sted by more than one master port, arbitrat ion logic selects the higher priority master an d grants it ownership of the slave port. all other masters requesting that slave por t are stalled until the higher priority master completes its transactions. requesting mast ers having equal prio rity are granted acces s to a slave port in round-robin fash ion, based upon the id of the last master to be granted access. the crossbar provides the following features: ? four master ports: ? e200z0h core instruction port ? e200z0h core complex load/store data port ? edma controller ? display control unit ? four slave ports: ? one flash port dedicated to the cpu ? platform sram ? quadspi serial flash controller ? one slave port combining: ? flash port dedicated to the display control unit and edma module ? graphics sram ? peripheral bridge ? 32-bit internal address bus, 32-bit internal data bus 1.5.4 enhanced direct memory access (edma) the edma module is a controller capable of performing complex data movements via 16 programmable channels, with minimal intervention from the host processor. the hardware mi cro architecture includes a dma engine, that performs source and destination address calculations, and the actual data moveme nt operations, along with an sram-based memory containing the transfer control descriptor s (tcd) for the channels. this implementation is utilized to minimize th e overall block size. th e edma module provides the following features: ? 16 channels support independent 8-, 16-, or 32-bit single value or block transfers. ? supports variable-sized queues and circular queues. ? source and destination addre ss registers are independently configured to post-increment or remain constant. ? each transfer is initiated by a peripheral, cpu, periodic timer interrupt, or edma channel request. ? each dma channel can optionally send an interrupt request to the cpu on completion of a single value or block transfer. ? dma transfers possible between sy stem memories, quadspi, dspis, i 2 c, adc, emios, and general purpose i/os (gpios). ? programmable dma channel mux allows assignment of any dma source to any availa ble dma channel with as many as 64 potential request sources. 1.5.5 inter-ic communications module (i 2 c) the i 2 c module features the following: ? as many as four i 2 c modules supported
mpc5606s microcontroller data sheet, rev. 8 overview freescale semiconductor 12 ? two-wire bi-directional serial bus for on-board communications ? compatibility with i 2 c bus standard ? multimaster operation ? software-programmable for one of 256 different serial clock frequencies ? software-selectable acknowledge bit ? interrupt-driven, byte-by-byte data transfer ? arbitration-lost interrupt with automatic mode switching from master to slave ? calling address identification interrupt ? start and stop signal generation/detection ? repeated start signal generation ? acknowledge bit generation/detection ? bus-busy detection 1.5.6 interrupt controller (intc) the intc provides priority-based preemptive scheduling of interrupt requests, suitable for stati cally scheduled hard real-time systems. for high-priority interrupt requests, the tim e from the assertion of the interrupt reque st from the peripher al to when the proc essor is executing the interrupt serv ice routine (isr) has been minimized. the intc provides a unique vector for each interrupt request source for quick determination of which isr needs to be ex ecuted. it also provides an ample number of priorities so tha t lower priority isrs do not dela y the execution of higher priority isrs. to allow the approp riate priorities for each source of interrupt request, the priority of each in terrupt request is software-configurable. when multiple tasks share a resour ce, coherent accesses to that resource need to be supported. the intc supports the priority ceiling protocol for coherent accesses. by pr oviding a modifiable priority mask, the pr iority can be raised temporarily so that all tasks which share the resource cannot preempt each other. multiple processors can assert interrupt requests to each ot her through software-settable in terrupt requests. these same software-settable interrupt requests also can be used to break the work involved in servicing an interrupt request into a high-priority portion and a low-priority portion. the high-priority por tion is initiated by a peripheral interrupt request, but then the isr asserts a software-settable interr upt request to finish the servicing in a lower priority isr. therefore these software-settable interrupt reques ts can be used instead of the peripheral is r scheduling a task through the rtos. the intc provides the following features: ? unique 9-bit vector for each of the possible 128 separate interrupt sources ? eight software triggerable interrupt sources ? 16 priority levels with fixed ha rdware arbitratio n within priority levels for each interrupt source ? ability to modify the isr or task priority ? modifying the priority can be used to implement the priority ceiling pr otocol for accessing shared resources ? external nmi directly accessing the main core critical interrupt mechanism ? 32 external interrupts 1.5.7 quadspi serial flash controller the quadspi module enables use of external serial flash memories supporting single, dual, and quad modes of operation. it features the following: ? memory mapping of external serial flash memory ? automatic serial flash read command generation by cpu, dma, or dcu read access on ahb bus ? supports single, dual, and qu ad serial flash read commands ? flexible buffering scheme to maximize read bandwidth of serial flash
overview mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 13 ? legacy mode allowing quadspi to be used as a standard dspi (no dsi or csi mode) 1.5.8 system integration unit (siu) the siu controls mcu, pad configuration, external interrupt, general purpose i/o (g pio) and internal peripheral multiplexing. the gpio features the following: ? as many as four levels of internal pin multiplexing, al lowing exceptional flexibility in the allocation of device functions for each package ? centralized general purpose input output (gpio) control of as many as 132 input/output pins (package dependent) ? all gpio pins can be independently configured to support pullup, pulldown, or no pull ? reading and writing to gpio supported both as individual pins and 16-bit-wide ports ? all peripheral pins can be alternatively configured as both general purpose input or output pins, except adc channels which support alternative configuration as general purpose inputs ? direct readback of the pin value supporte d on all digital output pins through the siu ? configurable digital input filter that can be applied to as many as 14 general purpose input pins for noise elimination on external interrupts ? register configuration protect ed against change with soft lock for temporary guard or hard lock to prevent modification until next reset 1.5.9 flash memory the mpc5606s microcontroller has the following flash memory features: ? as nuch as 1 mb of burst flash memory ? typical flash memory access time: 0 wa it state for buffer hits, 2 wait stat es for page buffer miss at 64 mhz ?two 4 ? 128-bit page buffers with programmable prefetch control ? one set of page buffers can be allocated for code-only, fixed partitions of code and data, all available for any access ? one set of page buffers allocated to display controller unit and the edma ? 64-bit ecc with single-bit correction, double-bit detection for data integrity ? 64 kb data flash memory ? separate 4 ? 16 kb flash block for eeprom emulation with prefetch buffer and 128-bit data access port ? small block flash memory arrangement to support f eatures such as boot block, operating system block ? hardware-managed flash memory writ es, erases and verify sequences ? censorship protection scheme to prevent flash memory content visibility ? separate dedicated 64 kb data fl ash memory for eeprom emulation ? four erase sectors each containing 16 kb of memory ? offers read-while-write functionality from main program space ? same data retention and progr am erase specification as main program flash memory array 1.5.10 sram the mpc5606s microcontrollers have as much as 48 kb ge neral-purpose on-chip sram with the following features: ? typical sram access time: 0 wait-state fo r reads and 32-bit writes; 1 wait state fo r 8- and 16-bit writes if back to back with a read to same memory block ? 32-bit ecc with single-bit correction, double bit detection for data integrity ? supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of memory ? user transparent ecc encoding and decodi ng for byte, half word, and word accesses
mpc5606s microcontroller data sheet, rev. 8 overview freescale semiconductor 14 ? separate internal power domain appl ied to full sram block, 8 kb sram block during standby modes to retain contents during low-power mode. 1.5.11 on-chip graphics sram the mpc5606s microcontroller has 160 kb on-chip graphics sram with the following features: ? usable as general purpose sram ? typical sram access time: 0 wait-st ate for reads and 32-bit writes ? supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of memory 1.5.12 memory protection unit (mpu) the mpu features the following: ? 12 region descriptors for per-master protection ? start and end address defined with 32-byte granularity ? overlapping regions supported ? protection attributes can optionally include process id ? protection offered for three concurrent read ports ? read and write attributes for all masters ? execute and supervisor/user mode attributes for processor masters 1.5.13 boot assist module (bam) the bam is a block of read-only memory that is programm ed once by freescale. the bam program is executed every time the mcu is started up or reset in normal mode. the bam supports different modes of booting. they are: ? booting from internal flash memory ? serial boot loading (a program is downloaded in to ram via flexcan or linflex and then executed) ? booting from external memory additionally the bam: ? enables and manages the transition of th e mcu from reset to user code execution ? configures device for serial bootload ? enables multiple bootcode starting locations out of rese t through implementation of search for valid reset configuration halfword 1.5.14 enhanced modular inpu t/output system (emios) mpc5606s microcontrollers have two emios modules?one with 16 channels and one with eight?with input/output channels supporting a range of 16-bit input capture, output compare, and pulse width modulation functions. the modules are configurable and can implement 8-channel, 16- bit input capture/output compare or 16-channel, 16-bit output pulse width modulation/input compare/output compare. as many as five additional channels are configurable as modulus counters. emios other features include: ? selectable clock source from main fmpll, auxiliary fmp ll, external 4?16 mhz oscill ator or 16 mhz internal rc oscillator ? timed i/o channels with 16-bit counter resolution ? buffered updates ? support for shifted pwm outputs to minimize occurrence of concurrent edges
overview mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 15 ? edge-aligned output pulse width modulation ? programmable pulse period and duty cycle ? supports 0% and 100% duty cycle ? shared or independent time bases ? programmable phase shift between channels ? selectable combination of pairs of emios outputs to support sound generation ? dma transfer support ? selectable clock source from the prim ary fmpll, auxiliary fmpll, external 4?16 mhz oscillator, or the 16 mhz internal rc oscillator. the channel configuration options for the 16- channel emios module are summarized in table 3 . the channel configuration options for the eigh t-channel emios module are summarized in table 4 . table 3. 16-channel emios module channel configuration channel mode channel number 8 ic/oc counter 9?15 ic/oc 16 pwm counter 17?22 pwm 23 pwm counter general purpose input/output xxxxx single action input capture xxxxx single action output compare xxxxx modulus counter buffered 1 1 modulus up and down counters to support driving local and global counter buses. xxx output pulse width and frequency modulation buffered xxx output pulse width modulation buffered x x x table 4. eight-channel emios module channel configuration channel mode channel number 16 pwm counter 17?22 pwm 23 pwm counter general purpose input/output x x x single action input capture x x x single action output compare x x x modulus counter buffered 1 1 modulus up and down counters to support driving local and global counter buses. xx output pulse width and frequency modulation buffered xxx output pulse width modulation buffered x x x
mpc5606s microcontroller data sheet, rev. 8 overview freescale semiconductor 16 1.5.15 analog-to-digital converter (adc) the adc features the following: ? 10-bit a/d resolution ? 0 to 5 v common mode conversion range ? supports conversions speeds of up to 1 s ? 16 internal and eight external channel support ? as many as 16 single-ended input channels ? all channels configured to have alternat e function as general purpose input/output pins ? 10-bit 3 counts accuracy (tue) ? external multiplexer support to increase as many as 23 channels ? automatic 1 8 multiplexer control ? external multiplexer connected to a dedicated input channel ? shared register between the eight external channels ? result register available for every non-multiplexed channel ? configurable left- or right-aligned result format ? supports for one-shot, scan, and injection conversion modes ? injection mode status bit implemented on adjacent 16-bit register for each result ? supports access to result and inject ion status with single 32-bit read ? independent enabling of function for channels: ?offset refresh ? conversion triggering support ? internal conversion triggering from periodic interrupt timer (pit) ? four configurable analog comparator channels offering range comparison with triggered alarm ? greater than ? less than ? out of range ? all unused analog inputs can be used as general purpose input and output pins ? power down mode ? optional support for dma transfer of results 1.5.16 deserial serial peripheral interface (dspi) the deserial serial peripheral interface (dspi) modules provide a sy nchronous serial interface fo r communication between the mpc5606s mcu and external devices. the dspi features the following: ? as many as two dspi modules ? full-duplex, synchronous transfers ? master or slave operation ? programmable master bit rates ? programmable clock polarity and phase ? end-of-transmission interrupt flag ? programmable transfer baud rate ? programmable data frames from 4 to 16 bits ? as many as six chip select lines available, depending on p ackage and pin multiplexing, enab le 64 external devices to be selected using external muxing from a single dspi
overview mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 17 ? eight clock and transfer attributes registers ? chip select strobe available as alternate function on one of the chip select pins for deglitching ? fifos for buffering as many as four tr ansfers on the transmit and receive side ? general purpose i/o functionality on pins when not used for spi ? queueing operation possible through use of edma 1.5.17 flexcan the mpc5606s mcu contains two controller area network (fle xcan) modules. the flexcan module is a communication controller implementing the can protocol according to bosch specifica tion version 2.0b. the can protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-tim e processing, reliable operation in the emi environment of a vehicle, cost-effectiveness, and required bandwidth. the flexcan modules offer the following: ? compliant with can protocol specification, version 2.0b active ? 64 mailboxes, each configurab le as transmit or receive ? mailboxes configurable while module remains synchronized to can bus ? transmit features ? supports configuration of multiple mailboxes to form message queues of scalable depth ? arbitration scheme according to me ssage id or message buffer number ? internal arbitration to guarantee no inner or outer priority inversion ? transmit abort procedure and notification ? receive features ? individual programmable filters for each mailbox ? eight mailboxes c onfigurable as a 6-entry receive fifo ? eight programmable accepta nce filters for receive fifo ? programmable clock source ? system clock ? direct oscillator clock to avoid pll jitter ? listen-only mode capabilities ? can sampler ? can catch the first message sent on the can network while the mpc5606s is stopped; this guarantees a clean startup of the system without missing messages on the can network ? can sampler is connected to one of the can rx pins 1.5.18 serial communication interface module (linflex) the mpc5606s devices include as many as two linflex modu les and support for lin master mode, lin slave mode, and uart mode. the modules are lin state mach ine-compliant to the lin 1.3 and 2.0 an d 2.1 specifications and handle lin frame transmission and reception without cpu in tervention. other features include: ? autonomous lin frame handling ? message buffer to store identif ier and as many as 8 data bytes ? supports message length as long as 64 bytes ? detection and flagging of lin errors ? sync field, delimiter, id parity, bit, framing, checksum, and timeout errors ? classic or extended checksum calculation
mpc5606s microcontroller data sheet, rev. 8 overview freescale semiconductor 18 ? configurable break duration as long as 36-bit times ? programmable baud rate prescalers (13-bit mantissa, 4-bit fractional) ? diagnostic features ? loopback ?self-test ? lin bus stuck dominant detection ? interrupt-driven operation with 16 interrupt sources ? lin slave mode features ? autonomous lin header handling ? autonomous lin response handling ? discarding of irrelevant lin respons es using as many as 16 id filters ? uart mode ? full-duplex operation ? standard non-return-to-zero (nrz) mark/space format ? data buffers with 4-byte receive, 4-byte transmit ? configurable word length (8-bit or 9-bit words) ? error detection and flagging ? parity, noise, and framing errors ? interrupt driven operation with four interrupt sources ? separate transmitter and r eceiver cpu interrupt sources ? 16-bit programmable baud-rate m odulus counter and 16-bit fractional ? two receiver wakeup methods 1.5.19 system clocks and clock generation modules the system clock on the mpc5606s can be derived from an exte rnal oscillator, an on-chip fmpll, or the internal 16 mhz oscillator. ? source system clock frequency can be changed via an on-chip programmable clock divider ( ? 1to ?? 2) ? additional programmable peripheral bus clock divider ratio ( ? 1 to ? 16) ? two on-chip fmplls?the primary module and an auxiliary module ? each fmpll features: ? input clock frequency from 4 mhz to 16 mhz ? lock detect circuitry continuously monitoring lock status ? loss of clock (loc) detection fo r reference and feedback clocks ? on-chip loop filter (for improved electromagnetic interference performance and reduction of number of external components required) ? support for frequency ramping from pll ? the primary fmpll module is for use as a system clock source; the auxiliary fmpll is available for use as an alternate, modulated or non-modulated clock source to emios modules and as alternate clock to the dcu for pixel clock generation ? the main oscillator provides the following features: ? input frequency range 4?16 mhz ? square-wave input mode ? oscillator input mode 3.3 v (5.0 v) ? automatic level control ? pll reference
overview mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 19 ? mpc5606s includes a 32 khz low-power external oscillator for sl ow execution, reduced power consumption, and real time clock ? dedicated internal 128 khz rc oscillator fo r low-power mode operation and self wakeup ? 10% accuracy across voltage and te mperature (after factory trimming) ? trimming registers to support improved accuracy with in-application calibration ? dedicated 16 mhz internal rc oscillator ? used as default clock source out of reset ? provides a clock for rapid startup from low-power modes ? provides a backup clock in the event of pll or external osci llator clock failure ? offers an independent clock source for the watchdog timer ? 5% accuracy across voltage and temp erature (after factory trimming) ? trimming registers to support frequency adjustment with in-application calibration 1.5.20 periodic interrupt timer module (pit) the pit features the following: ? four general-purpose interrupt timers ? as many as two dedicated interrupt timers for triggering adc conversions ? 32-bit counter resolution ? clocked by system clock frequency ? 32-bit counter for real time interrupt, clocked from main external oscillator 1.5.21 real time counter (rtc) the rtc supports wakeup from low-power modes or real time clock generation ? configurable resolution for different timeout periods ? 1 s resolution for >1 hour period ? 1 ms resolution for 2 second period ? selectable clock sources from external 32 khz crystal, ex ternal 4?16 mhz crystal, internal 128 khz rc oscillator, or divided internal 16 mhz rc oscillator 1.5.22 system timer module (stm) the stm is a 32-bit timer designed to support commonly require d system and application software timing functions. the stm includes a 32-bit up counter and fo ur 32-bit compare channels with a separate in terrupt source fo r each channel. the counter is driven by the system clock divided by an 8-bit prescale value (1 to 256). ? one 32-bit up counter with 8-bit prescaler ? four 32-bit compare channels ? independent interrupt source for each channel ? counter can be stopped in debug mode 1.5.23 software watchdog timer (swt) the watchdog features the following: ? watchdog can be activated by software or enabled out of reset ? supports normal or windowed mode ? watchdog timer value writable once after reset
mpc5606s microcontroller data sheet, rev. 8 overview freescale semiconductor 20 ? configurable response on timeout: reset, interrupt, or interrupt followed by reset ? selectable clock source for main system cl ock or internal 16 mhz rc oscillator clock 1.5.24 display control unit (dcu) the dcu is a display controller designed to drive tft lcd displays capable of driving screens with resolution as high as wide quarter video graphics array (wqvga), with 16 layers and four planes with real time alpha-blending. the dcu generates all the necessary signals required to drive the di splay: up to 24-bit rgb data bus, pixel clock, data enable, horizontal-sync and vertical-sync. the internal memory resources of the mp c5606s allow easy management of comple x graphics contents (pictures, icons, languages, fonts) on a color tft panel in up to wqvga sizes. al l the data fetches from internal and/or extern al memory are performed by the internal four-channel dma of the dcu provi ding a high speed/low latency access to the system backbone. control descriptors (cds) associ ated with each layer enable ef fective merging of different co lor formats into one plane to optimize use of internal memory buffers. a layer may be constr ucted from graphic content of various color formats including 1bpp, 2bpp, 4bpp, 8bpp, 16bpp, 24bpp, and 24bpp+alpha. the ability of the dcu to handle input data in formats as low as 1bpp, 2bpp, and 4bpp enables highly efficient use of internal me mory resources of the mpc5606s. a special tiled mode can be enabled on any of the 16 layers to repeat a pattern, optimizing graphic memory usage. a hardware cursor can be managed independently of the layers at blending level, increasing the efficient use of internal dcu resources. to secure the content of all cri tical information to be displayed, a safety mode can be activated to check the integrity of cri tical data along the whole system data path from the memory to the tft pads. the dcu features the following: ? display color depth: up to 24 bpp ? generation of all rgb and control signals for tft ? four-layer blending at each pixel position ? maximum number of input layers: 16 (fixed priority) ? dynamic look-up table (color and gamma look-up) ? ?? blending range: up to 256 levels ? transparency mode for font or single foreground color graphics ? gamma correction ? tiled mode on all the layers ? hardware cursor ? critical display content integrity monitoring for functional safety support ? internal direct memory access (dma) module to tran sfer data from internal and/or external memory 1.5.25 parallel data interface (pdi) the pdi is a digital interface used to receive extern al digital video or grap hic content into the dcu. the pdi input is directly injected into the dcu background plane fifo. when the pdi is activated, all the dcu synchronization is extracted from the external video stream to guarantee the synchronizati on of the two video sources. the pdi can be used to: ? connect a video camera out put directly to the pdi ? connect a secondary display driver as slave with a minimum of extra cost ? connect a device gathering various video sources ? provide flexibility to allow the dcu to be used in slave mode (external synchronization)
overview mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 21 the pdi features the following: ? supported color modes: ? 8-bit mono ? 8-bit color multiplexed ?rgb565 ? 16-bit/18-bit raw color ? supported synchronization modes: ? embedded itu-r bt.656-4 (rgb565 mode 2) ? hsync, vsync ? data enable ? direct interface with dc u background plane fifo ? synchronization generation for the dcu 1.5.26 liquid crystal display (lcd) driver the lcd driver module has two configurations al lowing a maximum of 160 or 228 lcd segments: ? as many as 40 frontplane driver s and four backplane drivers ? as many as 38 frontplane driv ers and six backplane drivers each segment is controlled and can be mask ed by a corresponding bit in the lcd ram. four to six multiplex modes (1/1, 1/2, 1/3, 1/4, 1/5, 1/6 duty) , and three bias (1/1, 1/2, 1/3) methods are available. all fron tplane and backplane pins can be multiplexed with other port functions. the lcd driver module f eatures the following: ? programmable frame clock generator from different clock sources: ? system clock ? internal rc oscillator ? programmable bias voltage level selector ? on-chip generation of all output voltage levels ? lcd voltage reference taken from main 5 v supply ? lcd ram ? contains the data to be displayed on the lcd ? data can be read from or written to the display ram at any time ? end-of-frame interrupt: ? optimize data refresh without visual artifacts ? selectable number of fram es between each interrupt ? contrast adjustment using programmable internal voltage reference ? remapping capability of four or six backplanes with frontplanes ? increases pin selection flexibility ? in low-power modes, lcd operation can be suspended under software control; the lcd can also operate in low-power modes, clocked by the internal 128 khz irc or external 32 khz crystal oscillator ? selectable output current boost during transitions 1.5.27 stepper motor controller (smc) the smc module is a pwm motor controller suitable to drive inst ruments in a cluster configuration or any other loads requiring a pwm signal. the motor controller has twelve pwm channels associated with two pins each (24 pins in total). the smc module includes the following features:
mpc5606s microcontroller data sheet, rev. 8 overview freescale semiconductor 22 ? 10/11-bit pwm counter ? 11-bit resolution with selectable pwm dithering function ? left-, right-, or center-aligned pwm ? output slew rate control ? output short-circuit detection this module is suited for, but not limited to, driving small stepper and air core motors used in instrumentation applications. this module can be used for other motor control or pwm applications that match the frequency, resolution, and output drive capabilities of the module. 1.5.28 stepper stall detect (ssd) the stepper stall detector (ssd) module provides a circuit to measure and integrate the induced voltage on the non-driven coil of a stepper motor using full steps when the gauge pointer is returning to zero (rtz). the ssd module features the following: ? programmable fu ll step state ? programmable integration polarity ? blanking (recirculation) state ? 16-bit integration accumulator register ? 16-bit modulus down counter with interrupt 1.5.29 sound generation logic (sgl) the sgl has two modes of operation: ? amplitude-modulated pwm mode for low-cost buzzers using any two emios channels: ? monophonic signal with amplitude control ? 8-bit amplitude resolution ? ability to mix any two emios channels ? requires simple external rc lowpass filter ? digital sample mode for higher quality sound using one emios channel and edma ? up to 10-bit audio amplitude resolution ? polyphonic sound synthesis ? playback of sample-based waveforms ? text-to-speech possibility ? requires external lowpass filter 1.5.30 ieee 1149.1 jtag controller (jtagc) jtagc features the following: ? backward compatible to standard jtag ie ee 1149.1-2001 test access port (tap) interface ? support for boundary scan testing 1.5.31 nexus development interface (ndi) nexus features the following: ? per ieee-isto 5001-2003 ? nexus 2 plus features supported
pinout and signal descriptions mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 23 ? static debug ? watchpoint messaging ? ownership trace messaging ? program trace messaging ? real time read/write of any internally memory-mapped resources through jtag pins ? overrun control, which selects whether to stall before nexus overruns or else keep executing and allow overwrite of information ? watchpoint triggering, watchpoint triggers program tracing ? configured via the ieee 1149.1 (jtag) port ? nexus auxiliary port supported on the 176 lqfp and 208-pin bga package for development only ? narrow auxiliary nexus port supporti ng support trace, with two mdo pins ? wide auxiliary nexus port supporting higher bandwidth trace, with four mdo pins 2 pinout and signal descriptions 2.1 144 lqfp package pinouts this section shows the pinouts for the 144-pin lqfp packages. caution any pins labeled ?nc? must not be connected to any external circuit.
mpc5606s microcontroller data sheet, rev. 8 pinout and signal descriptions freescale semiconductor 24 figure 2. 144-pin lqfp pinout for mpc5606s 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144-pin lqfp 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 nmi/gpio[72]/pf2 vdde_b vsse_b pcs2_0/emiosb19/rxd_1/gpio[28]/pb12 pcs1_0/emiosb18/txd_1/gpio[29]/pb13 vdd12 vss12 emiosb20/sck_0/gpio[25]/pb9 emiosb21/sout_0/gpio[24]/pb8 emiosb22/sin_0/gpio[23]/pb7 clkout/emiosb16/pcs0_0/gpio[103]/ph4 ma0/sck_1/gpio[20]/pb4 fabm/ma1/sout_1/gpio[21]/pb5 abs[0]/ma2/sin_1/gpio[22]/pb6 vdd12 vss12 vdda vssa xtal32/ans15/gpio[45]/pc15 extal32/ans14/gpio[44]/pc14 pcs0_1/ma2/ans13/gpio[43]/pc13 pcs1_1/ma1/ans12/gpio[42]/pc12 pcs2_1/ma0/ans11/gpio[41]/pc11 sound/ans10(mux)/gpio[40]/pc10 ans9/gpio[39]/pc9 ans8/gpio[38]/pc8 vdde_c vsse_c ans7/gpio[37]/pc7 ans6/gpio[36]/pc6 ans5/gpio[35]/pc5 ans4/gpio[34]/pc4 ans3/gpio[33]/pc3 ans2/gpio[32]/pc2 ans1/gpio[31]/pc1 ans0/gpio[30]/pc0 pa9/gpio[9]/dcu_g1/emiosb18/sda_2/fp14 pa8/gpio[8]/dcu_g0/emiosb23/scl_2/fp15 pa7/gpio[7]/dcu_r7/emiosa16/fp16 pa6/gpio[6]/dcu_r6/emiosa15/fp17 pa5/gpio[5]/dcu_r5/emiosa17/fp18 pa4/gpio[4]/dcu_r4/emiosa18/fp19 pa3/gpio[3]/dcu_r3/emiosa19/fp20 pa2/gpio[2]/dcu_r2/emiosa20/fp21 pa1/gpio[1]/dcu_r1/emiosa21/fp22 pa0/gpio[0]/dcu_r0/emiosa22/sound/fp23 vss12 vdd12 pf15/gpio[85]/sck_2/fp24 pf14/gpio[84]/sout_2/cantx_1/fp25 pf13/gpio[83]/sin_2/canrx_1/fp26 pf12/gpio[82]/emiosb16/pcs2_2/fp27 pf11/gpio[81]/emiosb23/pcs1_2/fp28 pf10/gpio[80]/emiosa16/pcs0_2/fp29 pg12/gpio[98]/emiosa23/sound/emiosa8/fp30 vsse_a vdde_a pf9/gpio[79]/scl_1/pcs0_1/txd_1/fp31 pf8/gpio[78]/sda_1/pcs1_1/rxd_1/fp32 pf7/gpio[77]/scl_0/pcs2_1/fp33 pf6/gpio[76]/sda_0/fp34 vss12 vdd12 pf5/gpio[75]/emiosa9/dcu_tag/fp35 pf4/gpio[74]/emiosa10/pdi7/fp36 pf3/gpio[73]/emiosa11/pdi6/fp37 pf1/gpio[71]/emiosa12/pdi5/emiosa21/fp38 pf0/gpio[70]/emiosa13/pdi4/emiosa22/fp39 pb2/gpio[18]/txd_0 pb3/gpio[19]/rxd_0 vsse_e vdde_e pb11/gpio[27]/cantx_1/pdi3/emiosa16 pb10gpio[26]//canrx_1/pdi2/emiosa23 pb0/gpio[16]/cantx_0/pdi1 pb1/gpio[17]/canrx_0/pdi0 vss12 vdd12 pe7/gpio[69]/m5c1p/ssd5_3/emiosa8 pe6/gpio[68]/m5c1m/ssd5_2/emiosa9 pe5/gpio[67]/m5c0p/ssd5_1/emiosa10 pe4/gpio[66]/m5c0m/ssd5_0/emiosa11 vssmc vddmc pe3/gpio[65]/m4c1p/ssd4_3/emiosa12 pe2/gpio[64]/m4c1m/ssd4_2/emiosa13 pe1/gpio[63]/m4c0p/ssd4_1/emiosa14 pe0/gpio[62]/m4c0m/ssd4_0/emiosa15 pd15/gpio[61]/m3c1p/ssd3_3 pd14/gpio[60]/m3c1m/ssd3_2 pd13/gpio[59]/m3c0p/ssd3_1 pd12/gpio[58/m3c0m/ssd3_0 vssmb vddmb pd11/gpio[57]/m2c1p/ssd2_3 pd10/gpio[56]/m2c1m/ssd2_2 pd9/gpio[55]/m2c0p/ssd2_1 pd8/gpio[54]/m2c0m/ssd2_0 pd7/gpio[53]/m1c1p/ssd1_3/emiosb16 pd6/gpio[52]/m1c1m/ssd1_2/emiosb17 pd5/gpio[51]/m1c0p/ssd1_1/emiosb18 pd4/gpio[50]/m1c0m/ssd1_0/emiosb19 vssma vddma pd3/gpio[49]/m0c1p/ssd0_3/emiosb20 pd2/gpio[48]/m0c1m/ssd0_2/emiosb21 pd1/gpio[47]/m0c0p/ssd0_1/emiosb22 pd0/gpio[46]/m0c0m/ssd0_0/emiosb23 (see detail inset) pa10 (see detail inset) pa11 (see detail inset) pa12 (see detail inset) pa13 (see detail inset) pa14 (see detail inset) pa15 vdde_a vsse_a (see detail inset) pg0 fp6/sda_3/dcu_b1/gpio[87]/pg1 (see detail inset) pg2 (see detail inset) pg3 (see detail inset) pg4 fp2/emiosa8/dcu_b5/gpio[91]/pg5 fp1/dcu_b6/gpio[92]/pg6 fp0/dcu_b7/gpio[93]/pg7 bp0/dcu_vsync/gpio[94]/pg8 bp1/dcu_hsync/gpio[95]/pg9 bp2/dcu_de/gpio[96]/pg10 bp3/dcu_pclk/gpio[97]/pg11 vlcd/gpio[104]/ph5 vddr vssr reset vrc_ctrl vpp xtal vssosc extal vsspll vddpll vreg_bypass tdi/gpio[100]/ph1 tdo/gpio[101]/ph2 tms/gpio[102]/ph3 tck/gpio[99]/ph0 detail: fp13/emiosb20/dcu_g2/gpio[10]/pa10 ? fp12/emiosa13/dcu_g3/gpio[11]/pa11 ? fp11/emiosa12/dcu_g4/gpio[12]/pa12 ? fp10/emiosa11/dcu_g5/gpio[13]/pa13 ? fp9/emiosa10/dcu_g6/gpio[14]/pa14 ? fp8/emiosa9/dcu_g7/gpio[15]/pa15 ? fp7/sound/scl_3/dcu_b0/gpio[86]/pg0 ? fp5/emiosb19/dcu_b2/gpio[88]/pg2 ? fp4/emiosb21/dcu_b3/gpio[89]/pg3 ? fp3/emiosb17/dcu_b4/gpio[90]/pg4 ?
pinout and signal descriptions mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 25 figure 3. 144-pin lqfppinout for mpc5604s 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 nmi/gpio[72]/pf2 vdde_b vsse_b pcs2_0/emiosb19/rxd_1/gpio[28]/pb12 pcs1_0/emiosb18/txd_1/gpio[29]/pb13 vdd12 vss12 emiosb20/sck_0/gpio[25]/pb9 emiosb21/sout_0/gpio[24]/pb8 emiosb22/sin_0/gpio[23]/pb7 clkout/emiosb16/pcs0_0/gpio[103]/ph4 ma0/sck_1/gpio[20]/pb4 fabm/ma1/sout_1/gpio[21]/pb5 abs[0]/ma2/sin_1/gpio[22]/pb6 vdd12 vss12 vdda vssa xtal32/ans15/gpio[45]/pc15 extal32/ans14/gpio[44]/pc14 pcs0_1/ma2/ans13/gpio[43]/pc13 pcs1_1/ma1/ans12/gpio[42]/pc12 pcs2_1/ma0/ans11/gpio[41]/pc11 sound/ans10(mux)/gpio[40]/pc10 ans9/gpio[39]/pc9 ans8/gpio[38]/pc8 vdde_c vsse_c ans7/gpio[37]/pc7 ans6/gpio[36]/pc6 ans5/gpio[35]/pc5 ans4/gpio[34]/pc4 ans3/gpio[33]/pc3 ans2/gpio[32]/pc2 ans1/gpio[31]/pc1 ans0/gpio[30]/pc0 pa9/gpio[9]/emiosb18/fp14 pa8/gpio[8]/emiosb23/fp15 pa7/gpio[7]/emiosa16/fp16 pa6/gpio[6]/emiosa15/fp17 pa5/gpio[5]/emiosa17/fp18 pa4/gpio[4]/emiosa18/fp19 pa3/gpio[3]/emiosa19/fp20 pa2/gpio[2]/emiosa20/fp21 pa1/gpio[1]/emiosa21/fp22 pa0/gpio[0]/emiosa22/sound/fp23 vss12 vdd12 pf15/gpio[85]/fp24 pf14/gpio[84]/cantx_1/fp25 pf13/gpio[83]/canrx_1/fp26 pf12/gpio[82]/emiosb16/fp27 pf11/gpio[81]/emiosb23/fp28 pf10/gpio[80]/emiosa16/fp29 pg12/gpio[98]/emiosa23/sound/emiosa8/fp30 vsse_a vdde_a pf9/gpio[79]/scl_1/pcs1_0/txd_1/fp31 pf8/gpio[78]/sda_1/pcs1_1/rxd_1/fp32 pf7/gpio[77]/scl_0/pcs2_1/fp33 pf6/gpio[76]/sda_0/fp34 vss12 vdd12 pf5/gpio[75]/emiosa9/fp35 pf4/gpio[74]/emiosa10/fp36 pf3/gpio[73]/emiosa11/fp37 pf1/gpio[71]/emiosa12/emiosa21/fp38 pf0/gpio[70]/emiosa13/emiosa22/fp39 pb2/gpio[18]/txd_0 pb3/gpio[19]/rxd_0 vsse_e vdde_e pb11/gpio[27]/cantx_1/emiosa16 pb10gpio[26]//canrx_1/emiosa23 pb0/gpio[16]/cantx_0 pb1/gpio[17]/canrx_0 vss12 vdd12 pe7/gpio[69]/m5c1p/ssd5_3/emiosa8 pe6/gpio[68]/m5c1m/ssd5_2/emiosa9 pe5/gpio[67]/m5c0p/ssd5_1/emiosa10 pe4/gpio[66]/m5c0m/ssd5_0/emiosa11 vssmc vddmc pe3/gpio[65]/m4c1p/ssd4_3/emiosa12 pe2/gpio[64]/m4c1m/ssd4_2/emiosa13 pe1/gpio[63]/m4c0p/ssd4_1/emiosa14 pe0/gpio[62]/m4c0m/ssd4_0/emiosa15 pd15/gpio[61]/m3c1p/ssd3_3 pd14/gpio[60]/m3c1m/ssd3_2 pd13/gpio[59]/m3c0p/ssd3_1 pd12/gpio[58/m3c0m/ssd3_0 vssmb vddmb pd11/gpio[57]/m2c1p/ssd2_3 pd10/gpio[56]/m2c1m/ssd2_2 pd9/gpio[55]/m2c0p/ssd2_1 pd8/gpio[54]/m2c0m/ssd2_0 pd7/gpio[53]/m1c1p/ssd1_3/emiosb16 pd6/gpio[52]/m1c1m/ssd1_2/emiosb17 pd5/gpio[51]/m1c0p/ssd1_1/emiosb18 pd4/gpio[50]/m1c0m/ssd1_0/emiosb19 vssma vddma pd3/gpio[49]/m0c1p/ssd0_3/emiosb20 pd2/gpio[48]/m0c1m/ssd0_2/emiosb21 pd1/gpio[47]/m0c0p/ssd0_1/emiosb22 pd0/gpio[46]/m0c0m/ssd0_0/emiosb23 (see detail inset) pa10 (see detail inset) pa11 (see detail inset) pa12 (see detail inset) pa13 (see detail inset) pa14 (see detail inset) pa15 vdde_a vsse_a (see detail inset) pg0 fp6/gpio[87]/pg1 (see detail inset) pg2 (see detail inset) pg3 (see detail inset) pg4 fp2/emiosa8/gpio[91]/pg5 fp1/gpio[92]/pg6 fp0/gpio[93]/pg7 bp0/gpio[94]/pg8 bp1/gpio[95]/pg9 bp2/gpio[96]/pg10 bp3/gpio[97]/pg11 vlcd/gpio[104]/ph5 vddr vssr reset vrc_ctrl vpp xtal vssosc extal vsspll vddpll vreg_bypass tdi/gpio[100]/ph1 tdo/gpio[101]/ph2 tms/gpio[102]/ph3 tck/gpio[99]/ph0 detail: fp13/emiosb20/gpio[10]/pa10 ? fp12/emiosa13/gpio[11]/pa11 ? fp11/emiosa12/gpio[12]/pa12 ? fp10/emiosa11/gpio[13]/pa13 ? fp9/emiosa10/gpio[14]/pa14 ? fp8/emiosa9/gpio[15]/pa15 ? fp7/sound/gpio[86]/pg0 ? fp5/emiosb19/gpio[88]/pg2 ? fp4/emiosb21/gpio[89]/pg3 ? fp3/emiosb17/gpio[90]/pg4 ? 144-pin lqfp mpc5604s
mpc5606s microcontroller data sheet, rev. 8 pinout and signal descriptions freescale semiconductor 26 figure 4. 144-pin lqfppinout for mpc5602s 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 nmi/gpio[72]/pf2 vdde_b vsse_b pcs2_0/emiosb19/rxd_1/gpio[28]/pb12 pcs1_0/emiosb18/txd_1/gpio[29]/pb13 vdd12 vss12 emiosb20/sck_0/gpio[25]/pb9 emiosb21/sout_0/gpio[24]/pb8 emiosb22/sin_0/gpio[23]/pb7 clkout/emiosb16/pcs0_0/gpio[103]/ph4 ma0/sck_1/gpio[20]/pb4 fabm/ma1/sout_1/gpio[21]/pb5 abs[0]/ma2/sin_1/gpio[22]/pb6 vdd12 vss12 vdda vssa xtal32/ans15/gpio[45]/pc15 extal32/ans14/gpio[44]/pc14 pcs0_1/ma2/ans13/gpio[43]/pc13 pcs1_1/ma1/ans12/gpio[42]/pc12 pcs2_1/ma0/ans11/gpio[41]/pc11 sound/ans10(mux)/gpio[40]/pc10 ans9/gpio[39]/pc9 ans8/gpio[38]/pc8 vdde_c vsse_c ans7/gpio[37]/pc7 ans6/gpio[36]/pc6 ans5/gpio[35]/pc5 ans4/gpio[34]/pc4 ans3/gpio[33]/pc3 ans2/gpio[32]/pc2 ans1/gpio[31]/pc1 ans0/gpio[30]/pc0 pa9/gpio[9]/emiosb18/fp14 pa8/gpio[8]/emiosb23/fp15 pa7/gpio[7]/emiosa16/fp16 pa6/gpio[6]/emiosa15/fp17 pa5/gpio[5]/emiosa17/fp18 pa4/gpio[4]/emiosa18/fp19 pa3/gpio[3]/emiosa19/fp20 pa2/gpio[2]/emiosa20/fp21 pa1/gpio[1]/emiosa21/fp22 pa0/gpio[0]/emiosa22/sound/fp23 vss12 vdd12 pf15/gpio[85]/fp24 pf14/gpio[84]/fp25 pf13/gpio[83]/fp26 pf12/gpio[82]/emiosb16/fp27 pf11/gpio[81]/emiosb23/fp28 pf10/gpio[80]/emiosa16/fp29 pg12/gpio[98]/emiosa23/sound/emiosa8/fp30 vsse_a vdde_a pf9/gpio[79]/scl_1/pcs1_0/txd_1/fp31 pf8/gpio[78]/sda_1/pcs1_1/rxd_1/fp32 pf7/gpio[77]/scl_0/pcs2_1/fp33 pf6/gpio[76]/sda_0/fp34 vss12 vdd12 pf5/gpio[75]/emiosa9/fp35 pf4/gpio[74]/emiosa10/fp36 pf3/gpio[73]/emiosa11/fp37 pf1/gpio[71]/emiosa12/emiosa21/fp38 pf0/gpio[70]/emiosa13/emiosa22/fp39 pb2/gpio[18]/txd_0 pb3/gpio[19]/rxd_0 vsse_e vdde_e pb11/gpio[27]/emiosa16 pb10gpio[26]/emiosa23 pb0/gpio[16]/cantx_0 pb1/gpio[17]/canrx_0 vss12 vdd12 pe7/gpio[69]/m5c1p/ssd5_3/emiosa8 pe6/gpio[68]/m5c1m/ssd5_2/emiosa9 pe5/gpio[67]/m5c0p/ssd5_1/emiosa10 pe4/gpio[66]/m5c0m/ssd5_0/emiosa11 vssmc vddmc pe3/gpio[65]/m4c1p/ssd4_3/emiosa12 pe2/gpio[64]/m4c1m/ssd4_2/emiosa13 pe1/gpio[63]/m4c0p/ssd4_1/emiosa14 pe0/gpio[62]/m4c0m/ssd4_0/emiosa15 pd15/gpio[61]/m3c1p/ssd3_3 pd14/gpio[60]/m3c1m/ssd3_2 pd13/gpio[59]/m3c0p/ssd3_1 pd12/gpio[58/m3c0m/ssd3_0 vssmb vddmb pd11/gpio[57]/m2c1p/ssd2_3 pd10/gpio[56]/m2c1m/ssd2_2 pd9/gpio[55]/m2c0p/ssd2_1 pd8/gpio[54]/m2c0m/ssd2_0 pd7/gpio[53]/m1c1p/ssd1_3/emiosb16 pd6/gpio[52]/m1c1m/ssd1_2/emiosb17 pd5/gpio[51]/m1c0p/ssd1_1/emiosb18 pd4/gpio[50]/m1c0m/ssd1_0/emiosb19 vssma vddma pd3/gpio[49]/m0c1p/ssd0_3/emiosb20 pd2/gpio[48]/m0c1m/ssd0_2/emiosb21 pd1/gpio[47]/m0c0p/ssd0_1/emiosb22 pd0/gpio[46]/m0c0m/ssd0_0/emiosb23 (see detail inset) pa10 (see detail inset) pa11 (see detail inset) pa12 (see detail inset) pa13 (see detail inset) pa14 (see detail inset) pa15 vdde_a vsse_a (see detail inset) pg0 fp6/gpio[87]/pg1 (see detail inset) pg2 (see detail inset) pg3 (see detail inset) pg4 fp2/emiosa8/gpio[91]/pg5 fp1/gpio[92]/pg6 fp0/gpio[93]/pg7 bp0/gpio[94]/pg8 bp1/gpio[95]/pg9 bp2/gpio[96]/pg10 bp3/gpio[97]/pg11 vlcd/gpio[104]/ph5 vddr vssr reset vrc_ctrl vpp xtal vssosc extal vsspll vddpll vreg_bypass tdi/gpio[100]/ph1 tdo/gpio[101]/ph2 tms/gpio[102]/ph3 tck/gpio[99]/ph0 detail: fp13/emiosb20/gpio[10]/pa10 ? fp12/emiosa13/gpio[11]/pa11 ? fp11/emiosa12/gpio[12]/pa12 ? fp10/emiosa11/gpio[13]/pa13 ? fp9/emiosa10/gpio[14]/pa14 ? fp8/emiosa9/gpio[15]/pa15 ? fp7/sound/gpio[86]/pg0 ? fp5/emiosb19/gpio[88]/pg2 ? fp4/emiosb21/gpio[89]/pg3 ? fp3/emiosb17/gpio[90]/pg4 ? 144-pin lqfp mpc5602s
pinout and signal descriptions mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 27 2.2 176 lqfp package pinout figure 5 shows the pinout for the 176-pin lqfp package. caution any pins labeled ?nc? must not be connected to any external circuit. figure 5. 176-pin lqfp pinout 176-pin lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 pa9/gpio[9]/dcu_g1/emiosb18/sda_2/fp14 pa8/gpio[8]/dcu_g0/emiosb23/scl_2/fp15 pa7/gpio[7]/dcu_r7/emiosa16/fp16 pa6/gpio[6]/dcu_r6/emiosa15/fp17 pa5/gpio[5]/dcu_r5/emiosa17/fp18 vsse_a vdde_a pa4/gpio[4]/dcu_r4/emiosa18/fp19 pa3/gpio[3]/dcu_r3/emiosa19/fp20 pa2/gpio[2]/dcu_r2/emiosa20/fp21 pa1/gpio[1]/dcu_r1/emiosa21/fp22 pa0/gpio[0]/dcu_r0/emiosa22/sound/fp23 vss12 vdd12 pf15/gpio[85]/sck_2/fp24 pf14/gpio[84]/sout_2/cantx_1/fp25 pf13/gpio[83]/sin_2/canrx_1/fp26 pf12/gpio[82]/emiosb16/pcs2_2/fp27 pf11/gpio[81]/emiosb23/pcs1_2/fp28 pf10/gpio[80]/emiosa16/pcs0_2/fp29 pg12/gpio[98]/emiosa23/sound/emiosa8/fp30 vsse_a vdde_a pf9/gpio[79]/scl_1/pcs0_1/txd_1/fp31 pf8/gpio[78]/sda_1/pcs1_1/rxd_1/fp32 pf7/gpio[77]/scl_0/pcs2_1/fp33 pf6/gpio[76]/sda_0/fp34 vss12 vdd12 pf5/gpio[75]/emiosa9/dcu_tag/fp35 pf4/gpio[74]/emiosa10/pdi7/fp36 pf3/gpio[73]/emiosa11/pdi6/fp37 pf1/gpio[71]/emiosa12/pdi5/emiosa21/fp38 pf0/gpio[70]/emiosa13/pdi4/emiosa22/fp39 pk1/gpio[122]/pdi13/emiosa17 pk0/gpio[121]/pdi12/emiosa18/dcu_tag pb2/gpio[18]/txd_0 pb3/gpio[19]/rxd_0 pj15/gpio[120]/pdi11/emiosa19 pj14/gpio[119]/pdi10/emiosa20 pj13/gpio[118]/pdi9/emiosb20 pj12/gpio[117]/pdi8/emiosb17 vsse_e vdde_e nmi/gpio[72]/pf2 vdde_b vsse_b pcs2_0/emiosb19/rxd_1/gpio[28]/pb12 pcs1_0/emiosb18/txd_1/gpio[29]/pb13 vdd12 vss12 emiosa15/sda_1/gpio[131]/pk10 emiosa14/scl_1/gpio[132]/pk11 emiosb20/sck_0/gpio[25]/pb9 emiosb21/sout_0/gpio[24]/pb8 emiosb22/sin_0/gpio[23]/pb7 canrx_0/pdi0/gpio[109]/pj4 cantx_0/pdi1/gpio[110]/pj5 emiosa22/canrx_1/pdi2/gpio[111]/pj6 emiosa21/cantx_1/pdi3/gpio[112]/pj7 clkout/emiosb16/pcs0_0/gpio[103]/ph4 ma0/sck_1/gpio[20]/pb4 fabm/ma1/sout_1/gpio[21]/pb5 vdde_b vsse_b abs[0]/ma2/sin_1/gpio[22]/pb6 vdd12 vss12 vdda vssa xtal32/ans15/gpio[45]/pc15 extal32/ans14/gpio[44]/pc14 pcs0_1/ma2/ans13/gpio[43]/pc13 pcs1_1/ma1/ans12/gpio[42]/pc12 pcs2_1/ma0/ans11/gpio[41]/pc11 sound/ans10(mux)/gpio[40]/pc10 ans9/gpio[39]/pc9 ans8/gpio[38]/pc8 vdde_c vsse_c ans7/gpio[37]/pc7 ans6/gpio[36]/pc6 ans5/gpio[35]/pc5 ans4/gpio[34]/pc4 ans3/gpio[33]/pc3 ans2/gpio[32]/pc2 ans1/gpio[31]/pc1 ans0/gpio[30]/pc0 pb11/gpio[27]/cantx_1/pdi3/emiosa16 pb10/gpio[26]/canrx_1/pdi2/emiosa23 pb0/gpio[16]/cantx_0/pdi1 pb1/gpio[17]/canrx_0/pdi0 pj11/gpio[116]/pdi7 pj10/gpio[115]/pdi6 pj9/gpio[114]/pdi5 pj8/gpio[113]/pdi4 vss12 vdd12 pj3/gpio[108]/pdi_pclk pj2/gpio[107]/pdi_vsync pj1/gpio[106]/pdi_hsync pj0/gpio[105]/pdi_de pe7/gpio[69]/m5c1p/ssd5_3/emiosa8 pe6/gpio[68]/m5c1m/ssd5_2/emiosa9 pe5/gpio[67]/m5c0p/ssd5_1/emiosa10 pe4/gpio[66]/m5c0m/ssd5_0/emiosa11 vssmc vddmc pe3/gpio[65]/m4c1p/ssd4_3/emiosa12 pe2/gpio[64]/m4c1m/ssd4_2/emiosa13 pe1/gpio[63]/m4c0p/ssd4_1/emiosa14 pe0/gpio[62]/m4c0m/ssd4_0/emiosa15 pd15/gpio[61]/m3c1p/ssd3_3 pd14/gpio[60]/m3c1m/ssd3_2 pd13/gpio[59]/m3c0p/ssd3_1 pd12/gpio[58]/m3c0m/ssd3_0 vssmb vddmb pd11/gpio[57]/m2c1p/ssd2_3 pd10/gpio[56]/m2c1m/ssd2_2 pd9/gpio[55]/m2c0p/ssd2_1 pd8/gpio[54]/m2c0m/ssd2_0 pd7/gpio[53]/m1c1p/ssd1_3/emiosb16 pd6/gpio[52]/m1c1m/ssd1_2/emiosb17 pd5/gpio[51]/m1c0p/ssd1_1/emiosb18 pd4/gpio[50]/m1c0m/ssd1_0/emiosb19 vssma vddma pd3/gpio[49]/m0c1p/ssd0_3/emiosb20 pd2/gpio[48]/m0c1m/ssd0_2/emiosb21 pd1/gpio[47]/m0c0p/ssd0_1/emiosb22 pd0/gpio[46]/m0c0m/ssd0_0/emiosb23 (see detail inset) pa10 (see detail inset) pa11 (see detail inset) pa12 (see detail inset) pa13 (see detail inset) pa14 (see detail inset) pa15 vdde_a vsse_a (see detail inset) pg0 (see detail inset) pg1 (see detail inset) pg2 (see detail inset) pg3 (see detail inset) pg4 (see detail inset) pg5 fp1/dcu_b6/gpio[92]/pg6 fp0/dcu_b7/gpio[93]/pg7 (see detail inset) pg8 (see detail inset) pg9 bp2/dcu_de/gpio[96]/pg10 (see detail inset) pg11 vlcd/gpio[104]/ph5 vddr vssr reset vrc_ctrl vpp xtal vssosc extal vsspll vddpll vreg_bypass pdi10/mcko/gpio[123]/pk2 pdi11/mseo/gpio[124]/pk3 pdi12/evto/gpio[125]/pk4 tdi/gpio[100]/ph1 pdi13/evti/gpio[126]/pk5 pdi14/mdo0/gpio[127]/pk6 tdo/gpio[101]/ph2 pdi15/mdo1/gpio[128]/pk7 tms/gpio[102]/ph3 pdi16/mdo2/gpio[129]/pk8 tck/gpio[99]/ph0 pdi17/mdo3/gpio[130]/pk9 detail: fp13/emiosb20/dcu_g2/gpio[10]/pa10 ? fp12/emiosa13/dcu_g3/gpio[11]/pa11 ? fp11/emiosa12/dcu_g4/gpio[12]/pa12 ? fp10/emiosa11/dcu_g5/gpio[13]/pa13 ? fp9/emiosa10/dcu_g6/gpio[14]/pa14 ? fp8/emiosa9/dcu_g7/gpio[15]/pa15 ? fp7/sound/scl_3/dcu_b0/gpio[86]/pg0 ? fp6/sda_3/dcu_b1/gpio[87]/pg1 ? fp5/emiosb19/dcu_b2/gpio[88]/pg2 ? fp4/emiosb21/dcu_b3/gpio[89]/pg3 ? fp3/emiosb17/dcu_b4/gpio[90]/pg4 ? fp2/emiosa8/dcu_b5/gpio[91]/pg5 ? bp0/dcu_vsync/gpio[94]/pg8 ? bp1/dcu_hsync/gpio[95]/pg9 ? bp3/dcu_pclk/gpio[97]/pg11 ?
mpc5606s microcontroller data sheet, rev. 8 pinout and signal descriptions freescale semiconductor 28 2.3 208 mapbga package ballmap figure 6 shows the ballmap for the 208-pin bga package. caution any pins labeled ?nc? must not be connected to any external circuit. figure 6. 208-pin mapbga pinout 1 2 3 4 5 6 7 8 9 1011121314 1516 a pa0 pj0 pj1 pj3 pj5 pj7 pj14 pf0 pf5 pk9 pk5 nc nc pf10 pf11 pf12 b pa1 vdde_a pj2 pj4 pj6 pj8 pj15 pf1 pf6 nc pk6 pk2 nc nc vdde_e pf13 c pa2 pa3 vdde_a pj9 pj10 pj12 pk0 pf3 pf7 nc pk7 pk3 nc vdde_e nc pf14 d pa4 pa5 pg0 vdd12 pj11 pj13 pk1 pf4 vdd12 pg12 pk8 pk4 vdd12 nc nc pf15 e pa 6 pa 7 p g 1 p g 2 nc nc nc nc f pa 8 pa 9 p g 3 p g 4 nc nc nc nc g pa10 pa11 pg5 pg6 vss vss vss vss nc pe7 pe1 nc h pa12 pa13 pa15 pg7 vss vss vss vss pe5 pe6 vddmc vssmc j reset pa14 pg8 pg10 vss vss vss vss pe4 pe2 pe0 pd8 k xtal vdde_a pg9 pg11 vss vss vss vss pe3 pd13 pd9 pd7 l vsspll vddpll nmi/pf2 mdo3 pd15 pd12 vddmb vssmb m extal vpp ph3 vreg bypass pd14 pd11 pd5 pd6 n vddr vlcd ph2 vdd12 pk11 pk10 pb8 pb5 pc13 pc9 pc6 pb11 vddma pd10 pd4 pd3 p vrc_ ctrl ph1 vdde_b mdo2 mdo1 pb13 pb7 pb4 pc12 pc8 pc5 pc3 pb10 nc pd2 pd1 r ph0 vdde_b evto pf9 ph4 pb12 pb6 pc15 pc11 pc7 pc4 pc2 pb3 pb2 vdde_b pd0 t mcko mseo evti pf8 mdo0 pb9 vdde_c pc14 pc10 vssa vdda pc1 pc0 pb1 pb0 vssma
pinout and signal descriptions mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 29 2.4 pad configuration during reset phases all pads have a fixed configuration under reset. during the startup phase, all pads are forced to tristate. after startup phase, all pads are floating with the following exceptions: ? pb[5] (fab) is pulldown. without external strong pullup the device starts fetching from flash. ? reset pad is driven low. this is released only after phase2 reset completion. ? main oscillator pads (extal, xtal) are tristate. ? nexus output pads (mdo[ n ], mcko, evto, mseo) are forced to output. ? the following pads are pullup: ?pb[6] ?ph[0] ?ph[1] ?ph[3] ?evti 2.5 voltage supply pins voltage supply pins are used to provide power to the device. two dedicated pins are used fo r 1.2 v regulator stabilization. there is a preferred startup sequ ence for devices in the mpc5606s family. that sequence is described in the next paragraphs. broadly, the supply voltages can be grouped as follows: ? vreg hv supply (v ddr ) ? generic i/o supply ?v dda ?v dde_a ?v dde_b ?v dde_c ?v dde_e ?v ddma ?v ddmb ?v ddmc ?v ddpll ?lv supply (v dd12 ) the preferred order of ra mp up is as follows: 1. generic i/o supply 2. vreg hv supply (v ddr should be the last hv supply to ramp up; it is also ok if all hv and generic i/o supplies including v ddr ramp up together) 3. lv supply the reason for following this sequence is to ensure that when vreg releases its lvds, the i/o and other hv segments are powered properly. this is important because the mpc 5606s does not monitor lv ds on i/o hv supplies.
mpc5606s microcontroller data sheet, rev. 8 pinout and signal descriptions freescale semiconductor 30 2.6 pad types the pads available for system pins and functional port pins are described in: ? the port pin summary table ? the pad type descriptions ? the description of the pad configuration registers in chapter 37, system integration unit lite (siul) ? the device data sheet 2.7 system pins the system pins are listed in table 6 . table 5. voltage supply pin descriptions supply pin function pin number 144 lqfp 176 lqfp vdd12 1 1 decoupling capacitors must be connected between these pins and the nearest v ss12 pin. 1.2 v core supply 42, 51, 103, 118 , 133 50, 67, 123, 148, 163 vdda 3.3 v/5 v adc supply source 53 69 vdde_a 3.3 v/5 v i/o supply 7, 124 7, 154, 170 vdde_b 3.3 v/5 v i/o supply 38 46, 64 vdde_c 3.3 v/5 v i/o supply 63 79 vdde_e 3.3 v/5 v i/o supply 109 133 vddma 2 2 all stepper motor supplies need to be at same level (3.3 v or 5 v). motor pads 5 v supply 77 93 vddmb 2 motor pads 5 v supply 87 103 vddmc 2 motor pads 5 v supply 97 113 vddpll 1.2 v pll supply 31 31 vddr vreg reg supply 22 22 vpp 3 3 this signal needs to be connected to ground during normal operation. 9 v?12 v flash test analog write signal 26 26 vss digital ground 8, 23, 39, 43, 52, 64, 104, 110, 119, 125, 134 8, 23, 47, 51, 68, 80, 124, 134, 149, 155, 164, 65, 171 vssa adc ground 54 70 vssma stepper motor ground 78 94 vssmb stepper motor ground 88 104 vssmc stepper motor ground 98 114 vssosc mhz oscillator ground 28 28 vsspll pll ground 30 30
pinout and signal descriptions mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 31 2.8 debug pins the debug pins are listed in table 7 . table 6. system pin descriptions system pin function i/o direction pad type reset config pin no. 144 lqfp 176 lqfp 208 mapbg a reset bidirectional reset with schmitt-trigger characteristics and noise filter. i/o m input, weak pullup 24 24 j1 xtal analog input of the oscillator amplifier circuit. needs to be grounded if oscillator bypass mode is used. ix ? 27 27 k1 extal analog output of the oscillator amplifier circuit. input for the clock generator in bypass mode. x ? 29 29 m1 vrc_ctrl vreg ballast control gain. ? ? ? 25 25 p1 vreg_ bypass 1 1 vreg_bypass should be pulled down externally. pin used for factory testing. i x ? 32 32 m4 table 7. debug pin descriptions debug pin function pad type i/o direction for debug reset config 1 pin number 144 lqfp 176 lqfp 2 208 mapbga muxed dedi- cated 3 tck jtag test clock s i input, pullup 36 43 r1 ? tdi jtag test data in s i input, pullup 33 36 p2 ? tdo jtag test data out m1 o output, none 34 39 n3 ? tms jtag test mode select s i input, pullup 35 41 m3 ? evti nexus event input m1 i input, pullup ? 37 a11 t3 evto nexus event output m1 o input, pullup ? 35 d12 r3 mcko nexus message data output 0 f o input, pullup ? 33 b12 t1 mdo0 nexus message data output 1 m o input, pullup ? 38 b11 t5
mpc5606s microcontroller data sheet, rev. 8 pinout and signal descriptions freescale semiconductor 32 mdo1 nexus message data output 2 m o input, pullup ? 40 c11 p5 mdo2 nexus message data output 3 m o input, pullup ? 42 d11 p4 mdo3 nexus message data output 4 m o input, pullup ? 44 a10 l4 mseo nexus message clock output m o input, pullup ? 34 c12 t2 1 see note for dedicated pi ns for 208 mapbga package. 2 on the 176 lqfp package, the nexus debug pins are multiplexed with other gpio. the 208 mapbga package provides dedicated nexus debug pins as well as multiplexed nexus debug pins. the multiplexing is described in the port pin summary table. 3 on the 208 mapbga package, the dedicated nexus debu g output pins (mdo[0:3] and mseo) may drive an unknown value (high or low) immediately after startup but be fore the first clock edge propagates through the device, instead of being weakly pulled low. this may cause high cu rrents if the pins are tied to a supply/ground in the application. if not used, these pins may be left unconnected. table 7. debug pin descriptions (continued) debug pin function pad type i/o direction for debug reset config 1 pin number 144 lqfp 176 lqfp 2 208 mapbga muxed dedi- cated 3
pinout and signal descriptions mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 33 2.9 port pin summary the functional port pins are listed in table 8 . table 8. port pin summary port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapbga pa[0] pcr[0] option 0 option 1 option 2 option 3 gpio[0] dcu_r0 emiosa[22] sound fp23 siul dcu pwm/timer sound i/o m1 none, none 135 165 a1 pa[1] pcr[1] option 0 option 1 option 2 option 3 gpio[1] dcu_r1 emiosa[21] ? fp22 siul dcu pwm/timer ? i/o m1 none, none 136 166 b1 pa[2] pcr[2] option 0 option 1 option 2 option 3 gpio[2] dcu_r2 emiosa[20] ? fp21 siul dcu pwm/timer ? i/o m1 none, none 137 167 c1 pa[3] pcr[3] option 0 option 1 option 2 option 3 gpio[3] dcu_r3 emiosa[19] ? fp20 siul dcu pwm/timer ? i/o m1 none, none 138 168 c2 pa[4] pcr[4] option 0 option 1 option 2 option 3 gpio[4] dcu_r4 emiosa[18] ? fp19 siul dcu pwm/timer ? i/o m1 none, none 139 169 d1 pa[5] pcr[5] option 0 option 1 option 2 option 3 gpio[5] dcu_r5 emiosa[17] ? fp18 siul dcu pwm/timer ? i/o m1 none, none 140 172 d2 pa[6] pcr[6] option 0 option 1 option 2 option 3 gpio[6] dcu_r6 emiosa[15] ? fp17 siul dcu pwm/timer ? i/o m1 none, none 141 173 e1 pa[7] pcr[7] option 0 option 1 option 2 option 3 gpio[7] dcu_r7 emiosa[16] ? fp16 siul dcu pwm/timer ? i/o m1 none, none 142 174 e2
mpc5606s microcontroller data sheet, rev. 8 pinout and signal descriptions freescale semiconductor 34 pa[8] pcr[8] option 0 option 1 option 2 option 3 gpio[8] dcu_g0 emiosb[23] scl_2 fp15 siul dcu pwm/timer i 2 c_2 i/o m1 none, none 143 175 f1 pa[9] pcr[9] option 0 option 1 option 2 option 3 gpio[9] dcu_g1 emiosb[18] sda_2 fp14 siul dcu pwm/timer i 2 c_2 i/o m1 none, none 144 176 f2 pa[10] pcr[10] option 0 option 1 option 2 option 3 gpio[10] dcu_g2 emiosb[20] ? fp13 siul dcu pwm/timer ? i/o m1 none, none 11g1 pa[11] pcr[11] option 0 option 1 option 2 option 3 gpio[11] dcu_g3 emiosa[13] ? fp12 siul dcu pwm/timer ? i/o m1 none, none 22g2 pa[12] pcr[12] option 0 option 1 option 2 option 3 gpio[12] dcu_g4 emiosa[12] ? fp11 siul dcu pwm/timer ? i/o m1 none, none 33h1 pa[13] pcr[13] option 0 option 1 option 2 option 3 gpio[13] dcu_g5 emiosa[11] ? fp10 siul dcu pwm/timer ? i/o m1 none, none 44h2 pa[14] pcr[14] option 0 option 1 option 2 option 3 gpio[14] dcu_g6 emiosa[10] ? fp9 siul dcu pwm/timer ? i/o m2 none, none 55j2 pa[15] pcr[15] option 0 option 1 option 2 option 3 gpio[15] dcu_g7 emiosa[9] ? fp8 siul dcu pwm/timer ? i/o m1 none, none 66h3 table 8. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapbga
pinout and signal descriptions mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 35 pb[0] pcr[16] option 0 option 1 option 2 option 3 gpio[16] cantx_0 pdi1 ? ?siul flexcan_0 pdi ? i/o m1 none, none 106 130 t15 pb[1] pcr[17] option 0 option 1 option 2 option3 gpio[17] canrx_0 pdi0 ? ?siul flexcan_0 pdi ? i/o s none, none 105 129 t14 pb[2] pcr[18] option 0 option 1 option 2 option3 gpio[18] txd_0 ? ? ?siul linflex_0 ? ? i/o s none, none 112 140 r14 pb[3] pcr[19] option 0 option 1 option 2 option3 gpio[19] rxd_0 ? ? ?siul linflex_0 ? ? i/o s none, none 111 139 r13 pb[4] pcr[20] option 0 option 1 option 2 option 3 gpio[20] sck_1 ma0 ? ?siul dspi_1 adc ? i/o m1 none, none 48 62 p8 pb[5] pcr[21] option 0 option 1 option 2 option 3 gpio[21] sout_1 ma1 fabm ?siul dspi_1 adc control i/o m1 input, pulldown 49 63 n8 pb[6] pcr[22] option 0 option 1 option 2 option 3 gpio[22] sin_1 ma2 abs[0] ?siul dspi_1 adc control i/o s input, pullup 50 66 r7 pb[7] pcr[23] option 0 option 1 option 2 option 3 gpio[23] sin_0 emiosb[22] ? ?siul dspi_0 pwm/timer ? i/o s none, none 46 56 p7 table 8. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapbga
mpc5606s microcontroller data sheet, rev. 8 pinout and signal descriptions freescale semiconductor 36 pb[8] pcr[24] option 0 option 1 option 2 option 3 gpio[24] sout_0 emiosb[21] ? ?siul dspi_0 pwm/timer ? i/o m1 none, none 45 55 n7 pb[9] pcr[25] option 0 option 1 option 2 option 3 gpio[25] sck_0 emiosb[20] ? ?siul dspi_0 pwm/timer ? i/o m1 none, none 44 54 t6 pb[10] pcr[26] option 0 option 1 option 2 option 3 gpio[26] canrx_1 pdi2 emiosa[23] ?siul flexcan_1 pdi pwm/timer i/o s none, none 107 131 p13 pb[11] pcr[27] option 0 option 1 option 2 option 3 gpio[27] cantx_1 pdi3 emiosa[16] ?siul flexcan_1 pdi pwm/timer i/o m1 none, none 108 132 n12 pb[12] pcr[28] option 0 option 1 option 2 option 3 gpio[28] rxd_1 emiosb[19] pcs2_0 ?siul linflex_1 pwm/timer dspi_0 i/o s none, none 40 48 r6 pb[13] pcr[29] option 0 option 1 option 2 option 3 gpio[29] txd_1 emiosb[18] pcs1_0 ?siul linflex_1 pwm/timer dspi_0 i/o s none, none 41 49 p6 pb[14] ? ? reserved ? ? ? ? ? ? ? ? pb[15] ? ? reserved ? ? ? ? ? ? ? ? pc[0] pcr[30] option 0 option 1 option 2 option 3 gpio[30] ? ? ? ans[0] siul ? ? ? i/o j none, none 72 88 t13 pc[1] pcr[31] option 0 option 1 option 2 option 3 gpio[31] ? ? ? ans[1] siul ? ? ? i/o j none, none 71 87 t12 table 8. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapbga
pinout and signal descriptions mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 37 pc[2] pcr[32] option 0 option 1 option 2 option 3 gpio[32] ? ? ? ans[2] siul ? ? ? i/o j none, none 70 86 r12 pc[3] pcr[33] option 0 option 1 option 2 option 3 gpio[33] ? ? ? ans[3] siul ? ? ? i/o j none, none 69 85 p12 pc[4] pcr[34] option 0 option 1 option 2 option 3 gpio[34] ? ? ? ans[4] siul ? ? ? i/o j none, none 68 84 r11 pc[5] pcr[35] option 0 option 1 option 2 option 3 gpio[35] ? ? ? ans[5] siul ? ? ? i/o j none, none 67 83 p11 pc[6] pcr[36] option 0 option 1 option 2 option 3 gpio[36] ? ? ? ans[6] siul ? ? ? i/o j none, none 66 82 n11 pc[7] pcr[37] option 0 option 1 option 2 option 3 gpio[37] ? ? ? ans[7] siul ? ? ? i/o j none, none 65 81 r10 pc[8] pcr[38] option 0 option 1 option 2 option 3 gpio[38] ? ? ? ans[8] siul ? ? ? i/o j none, none 62 78 p10 pc[9] pcr[39] option 0 option 1 option 2 option 3 gpio[39] ? ? ? ans[9] siul ? ? ? i/o j none, none 61 77 n10 table 8. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapbga
mpc5606s microcontroller data sheet, rev. 8 pinout and signal descriptions freescale semiconductor 38 pc[10] pcr[40] option 0 option 1 option 2 option 3 gpio[40] ? sound ? ans[10] siul ? sgl ? i/o j none, none 60 76 t9 pc[11] pcr[41] option 0 option 1 option 2 option 3 gpio[41] ? ma0 pcs2_1 ans[11] siul ? adc dspi_1 i/o j none, none 59 75 r9 pc[12] pcr[42] option 0 option 1 option 2 option 3 gpio[42] ? ma1 pcs1_1 ans[12] siul ? adc dspi_1 i/o j none, none 58 74 p9 pc[13] pcr[43] option 0 option 1 option 2 option 3 gpio[43] ? ma2 pcs0_1 ans[13] siul ? adc dspi_1 i/o j none, none 57 73 n9 pc[14] pcr[44] option 0 option 1 option 2 option 3 gpio[44] ? ? ? ans[14] extal32 siul ? ? ? i/o j none, none 56 72 t8 pc[15] pcr[45] option 0 option 1 option 2 option 3 gpio[45] ? ? ? ans[15] xtal32 siul ? ? ? i/o j none, none 55 71 r8 pd[0] pcr[46] option 0 option 1 option 2 option 3 gpio[46] m0c0m ssd0_0 emiosb[23] ?siul smc ssd pwm/timer i/o smd none, none 73 89 r16 pd[1] pcr[47] option 0 option 1 option 2 option 3 gpio[47] m0c0p ssd0_1 emiosb[22] ?siul smc ssd pwm/timer i/o smd none, none 74 90 p16 table 8. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapbga
pinout and signal descriptions mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 39 pd[2] pcr[48] option 0 option 1 option 2 option 3 gpio[48] m0c1m ssd0_2 emiosb[21] ?siul smc ssd pwm/timer i/o smd none, none 75 91 p15 pd[3] pcr[49] option 0 option 1 option 2 option 3 gpio[49] m0c1p ssd0_3 emiosb[20] ?siul smc ssd pwm/timer i/o smd none, none 76 92 n16 pd[4] pcr[50] option 0 option 1 option 2 option 3 gpio[50] m1c0m ssd1_0 emiosb[19] ?siul smc ssd pwm/timer i/o smd none, none 79 95 n15 pd[5] pcr[51] option 0 option 1 option 2 option 3 gpio[51] m1c0p ssd1_1 emiosb[18] ?siul smc ssd pwm/timer i/o smd none, none 80 96 m15 pd[6] pcr[52] option 0 option 1 option 2 option 3 gpio[52] m1c1m ssd1_2 emiosb[17] ?siul smc ssd pwm/timer i/o smd none, none 81 97 m16 pd[7] pcr[53] option 0 option 1 option 2 option 3 gpio[53] m1c1p ssd1_3 emiosb[16] ?siul smc ssd pwm/timer i/o smd none, none 82 98 k16 pd[8] pcr[54] option 0 option 1 option 2 option 3 gpio[54] m2c0m ssd2_0 ? ?siul smc ssd ? i/o smd none, none 83 99 j16 pd[9] pcr[55] option 0 option 1 option 2 option 3 gpio[55] m2c0p ssd2_1 ? ?siul smc ssd ? i/o smd none, none 84 100 k15 table 8. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapbga
mpc5606s microcontroller data sheet, rev. 8 pinout and signal descriptions freescale semiconductor 40 pd[10] pcr[56] option 0 option 1 option 2 option 3 gpio[56] m2c1m ssd2_2 ? ?siul smc ssd ? i/o smd none, none 85 101 n14 pd[11] pcr[57] option 0 option 1 option 2 option 3 gpio[57] m2c1p ssd2_3 ? ?siul smc ssd ? i/o smd none, none 86 102 m14 pd[12] pcr[58] option 0 option 1 option 2 option 3 gpio[58] m3c0m ssd3_0 ? ?siul smc ssd ? i/o smd none, none 89 105 l14 pd[13] pcr[59] option 0 option 1 option 2 option 3 gpio[59] m3c0p ssd3_1 ? ?siul smc ssd ? i/o smd none, none 90 106 k14 pd[14] pcr[60] option 0 option 1 option 2 option 3 gpio[60] m3c1m ssd3_2 ? ?siul smc ssd ? i/o smd none, none 91 107 m13 pd[15] pcr[61] option 0 option 1 option 2 option 3 gpio[61] m3c1p ssd3_3 ? ?siul smc ssd ? i/o smd none, none 92 108 l13 pe[0] pcr[62] option 0 option 1 option 2 option 3 gpio[62] m4c0m ssd4_0 emiosa[15] ?siul smc ssd pwm/timer i/o smd none, none 93 109 j15 pe[1] pcr[63] option 0 option 1 option 2 option 3 gpio[63] m4c0p ssd4_1 emiosa[14] ?siul smc ssd pwm/timer i/o smd none, none 94 110 g15 table 8. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapbga
pinout and signal descriptions mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 41 pe[2] pcr[64] option 0 option 1 option 2 option 3 gpio[64] m4c1m ssd4_2 emiosa[13] ?siul smc ssd pwm/timer i/o smd none, none 95 111 j14 pe[3] pcr[65] option 0 option 1 option 2 option 3 gpio[65] m4c1p ssd4_3 emiosa[12] ?siul smc ssd pwm/timer i/o smd none, none 96 112 k13 pe[4] pcr[66] option 0 option 1 option 2 option 3 gpio[66] m5c0m ssd5_0 emiosa[11] ?siul smc ssd pwm/timer i/o smd none, none 99 115 j13 pe[5] pcr[67] option 0 option 1 option 2 option 3 gpio[67] m5c0p ssd5_1 emiosa[10] ?siul smc ssd pwm/timer i/o smd none, none 100 116 h13 pe[6] pcr[68] option 0 option 1 option 2 option 3 gpio[68] m5c1m ssd5_2 emiosa[9] ?siul smc ssd pwm/timer i/o smd none, none 101 117 h14 pe[7] pcr[69] option 0 option 1 option 2 option 3 gpio[69] m5c1p ssd5_3 emiosa[8] ?siul smc ssd pwm/timer i/o smd none, none 102 118 g14 pe[8] ? ? reserved ? ? ? ? ? ? ? ? pe[9] ? ? reserved ? ? ? ? ? ? ? ? pe[10] ? ? reserved ? ? ? ? ? ? ? ? pe[11] ? ? reserved ? ? ? ? ? ? ? ? pe[12] ? ? reserved ? ? ? ? ? ? ? ? pe[13] ? ? reserved ? ? ? ? ? ? ? ? pe[14] ? ? reserved ? ? ? ? ? ? ? ? pe[15] ? ? reserved ? ? ? ? ? ? ? ? table 8. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapbga
mpc5606s microcontroller data sheet, rev. 8 pinout and signal descriptions freescale semiconductor 42 pf[0] pcr[70] option 0 option 1 option 2 option 3 gpio[70] emiosa[13] pdi4 emiosa[22] fp39 siul pwm/timer pdi pwm/timer i/o s none, none 113 143 a8 pf[1] pcr[71] option 0 option 1 option 2 option 3 gpio[71] emiosa[12] pdi5 emiosa[21] fp38 siul pwm/timer pdi pwm/timer i/o s none, none 114 144 b8 pf[2] pcr[72] option 0 option 1 option 2 option 3 gpio[72] nmi ? ? ?siul nmi ? ? i/o s none, none 37 45 l3 pf[3] pcr[73] option 0 option 1 option 2 option 3 gpio[73] emiosa[11] pdi6 ? fp37 siul pwm/timer pdi ? i/o m1 none, none 115 145 c8 pf[4] pcr[74] option 0 option 1 option 2 option 3 gpio[74] emiosa[10] pdi7 ? fp36 siul pwm/timer pdi ? i/o m1 none, none 116 146 d8 pf[5] pcr[75] option 0 option 1 option 2 option 3 gpio[75] emiosa[9] dcu_tag ? fp35 siul pwm/timer dcu ? i/o m1 none, none 117 147 a9 pf[6] pcr[76] option 0 option 1 option 2 option 3 gpio[76] sda_0 ? ? fp34 siul i 2 c_0 ? ? i/o s none, none 120 150 b9 pf[7] pcr[77] option 0 option 1 option 2 option 3 gpio[77] scl_0 pcs2_1 ? fp33 siul i 2 c_0 dspi_1 ? i/o s none, none 121 151 c9 table 8. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapbga
pinout and signal descriptions mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 43 pf[8] pcr[78] option 0 option 1 option 2 option 3 gpio[78] sda_1 pcs1_1 rxd_1 fp32 siul i 2 c_1 dspi_1 linflex_1 i/o s none, none 122 152 t4 pf[9] pcr[79] option 0 option 1 option 2 option 3 gpio[79] scl_1 pcs0_1 txd_1 fp31 siul i 2 c_1 dspi_1 linflex_1 i/o s none, none 123 153 r4 pf[10] pcr[80] option 0 option 1 option 2 option 3 gpio[80] emiosa[16] pcs0_2 ? fp29 siul pwm/timer quadspi ? i/o m1 none, none 127 157 a14 pf[11] pcr[81] option 0 option 1 option 2 option 3 gpio[81] emiosb[23] io2/pcs1_2 6 ? fp28 siul pwm/timer quadspi ? i/o m1 none, none 128 158 a15 pf[12] pcr[82] option 0 option 1 option 2 option 3 gpio[82] emiosb[16] io3/pcs2_2 6 ? fp27 siul pwm/timer quadspi ? i/o m1 none, none 129 159 a16 pf[13] pcr[83] option 0 option 1 option 2 option 3 gpio[83] io0/sin_2 6 canrx_1 ? fp26 siul quadspi flexcan_1 ? i/o m1 none, none 130 160 b16 pf[14] pcr[84] option 0 option 1 option 2 option 3 gpio[84] io1/sout_2 6 cantx_1 ? fp25 siul quadspi flexcan_1 ? i/o m1 none, none 131 161 c16 pf[15] pcr[85] option 0 option 1 option 2 option 3 gpio[85] sck_2 ? ? fp24 siul quadspi ? ? i/o f none, none 132 162 d16 table 8. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapbga
mpc5606s microcontroller data sheet, rev. 8 pinout and signal descriptions freescale semiconductor 44 pg[0] pcr[86] option 0 option 1 option 2 option 3 gpio[86] dcu_b0 scl_3 sound fp7 siul dcu i 2 c_3 sgl i/o m2 none, none 99d3 pg[1] pcr[87] option 0 option 1 option 2 option 3 gpio[87] dcu_b1 sda_3 ? fp6 siul dcu i 2 c_3 ? i/o m1 none, none 10 10 e3 pg[2] pcr[88] option 0 option 1 option 2 option 3 gpio[88] dcu_b2 emiosb[19] ? fp5 siul dcu pwm/timer ? i/o m2 none, none 11 11 e4 pg[3] pcr[89] option 0 option 1 option 2 option 3 gpio[89] dcu_b3 emiosb[21] ? fp4 siul dcu pwm/timer ? i/o m1 none, none 12 12 f3 pg[4] pcr[90] option 0 option 1 option 2 option 3 gpio[90] dcu_b4 emiosb[17] ? fp3 siul dcu pwm/timer ? i/o m2 none, none 13 13 f4 pg[5] pcr[91] option 0 option 1 option 2 option 3 gpio[91] dcu_b5 emiosa[8] ? fp2 siul dcu pwm/timer ? i/o m1 none, none 14 14 g3 pg[6] pcr[92] option 0 option 1 option 2 option 3 gpio[92] dcu_b6 ? ? fp1 siul dcu ? ? i/o m2 none, none 15 15 g4 pg[7] pcr[93] option 0 option 1 option 2 option 3 gpio[93] dcu_b7 ? ? fp0 siul dcu ? ? i/o m1 none, none 16 16 h4 table 8. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapbga
pinout and signal descriptions mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 45 pg[8] pcr[94] option 0 option 1 option 2 option 3 gpio[94] dcu_vsync ? ? bp0 siul dcu ? ? i/o m2 input, none 17 17 j3 pg[9] pcr[95] option 0 option 1 option 2 option 3 gpio[95] dcu_hsync ? ? bp1 siul dcu ? ? i/o m1 input, none 18 18 k3 pg[10] pcr[96] option 0 option 1 option 2 option 3 gpio[96] dcu_de ? ? bp2 siul dcu ? ? i/o m2 none, none 19 19 j4 pg[11] pcr[97] option 0 option 1 option 2 option 3 gpio[97] dcu_pclk ? ? bp3 siul dcu ? ? i/o m1 none, none 20 20 k4 pg[12] pcr[98] option 0 option 1 option 2 option 3 gpio[98] emiosa[23] sound emiosa[8] fp30 siul pwm/timer sgl pwm/timer i/o s none, none 126 156 d10 pg[13] ? ? reserved ? ? ? ? ? ? ? ? pg[14] ? ? reserved ? ? ? ? ? ? ? ? pg[15] ? ? reserved ? ? ? ? ? ? ? ? ph[0] 7 pcr[99] option 0 option 1 option 2 option 3 gpio[99] tck ? ? ?siul jtag ? ? i/o s input, pullup 36 43 r1 ph[1] 7 pcr[100] option 0 option 1 option 2 option 3 gpio[100] tdi ? ? ?siul jtag ? ? i/o s input, pullup 33 36 p2 table 8. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapbga
mpc5606s microcontroller data sheet, rev. 8 pinout and signal descriptions freescale semiconductor 46 ph[2] 7 pcr[101] option 0 option 1 option 2 option 3 gpio[101] tdo ? ? ?siul jtag ? ? i/o m1 output, none 34 39 n3 ph[3] 7 pcr[102] option 0 option 1 option 2 option 3 gpio[102] tms ? ? ?siul jtag ? ? i/o s input, pullup 35 41 m3 ph[4] pcr[103] option 0 option 1 option 2 option 3 gpio[103] pcs0_0 emiosb[16] clkout ?siul dspi_0 pwm/timer control i/o f none, none 47 61 r5 ph[5] pcr[104] option 0 option 1 option 2 option 3 gpio[104] vlcd 8 ? ? ?siul lcd ? ? i/o s none, none 21 21 n2 ph[6] ? ? reserved ? ? ? ? ? ? ? ? ph[7] ? ? reserved ? ? ? ? ? ? ? ? ph[8] ? ? reserved ? ? ? ? ? ? ? ? ph[9] ? ? reserved ? ? ? ? ? ? ? ? ph[10] ? ? reserved ? ? ? ? ? ? ? ? ph[11] ? ? reserved ? ? ? ? ? ? ? ? ph[12] ? ? reserved ? ? ? ? ? ? ? ? ph[13] ? ? reserved ? ? ? ? ? ? ? ? ph[14] ? ? reserved ? ? ? ? ? ? ? ? ph[15] ? ? reserved ? ? ? ? ? ? ? ? pj[0] pcr[105] option 0 option 1 option 2 option 3 gpio[105] pdi_de ? ? ?siul pdi ? ? i/o s none, none ?119 a2 table 8. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapbga
pinout and signal descriptions mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 47 pj[1] pcr[106] option 0 option 1 option 2 option 3 gpio[106] pdi_hsync ? ? ?siul pdi ? ? i/o s none, none ?120 a3 pj[2] pcr[107] option 0 option 1 option 2 option 3 gpio[107] pdi_vsync ? ? ?siul pdi ? ? i/o s none, none ?121 b3 pj[3] pcr[108] option 0 option 1 option 2 option 3 gpio[108] pdi_pclk ? ? ?siul pdi ? ? i/o m1 none, none ?122 a4 pj[4] pcr[109] option 0 option 1 option 2 option 3 gpio[109] pdi[0] canrx_0 ? ?siul pdi flexcan_0 ? i/o s none, none ?57 b4 pj[5] pcr[110] option 0 option 1 option 2 option 3 gpio[110] pdi[1] cantx_0 ? ?siul pdi flexcan_0 ? i/o m1 none, none ?58 a5 pj[6] pcr[111] option 0 option 1 option 2 option 3 gpio[111] pdi[2] canrx_1 emiosa[22] ?siul pdi flexcan_1 pwm/timer i/o s none, none ?59 b5 pj[7] pcr[112] option 0 option 1 option 2 option 3 gpio[112] pdi[3] cantx_1 emiosa[21] ?siul pdi flexcan_1 pwm/timer i/o m1 none, none ?60 a6 pj[8] pcr[113] option 0 option 1 option 2 option 3 gpio[113] pdi[4] ? ? ?siul pdi ? ? i/o s none, none ?125 b6 table 8. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapbga
mpc5606s microcontroller data sheet, rev. 8 pinout and signal descriptions freescale semiconductor 48 pj[9] pcr[114] option 0 option 1 option 2 option 3 gpio[114] pdi[5] ? ? ?siul pdi ? ? i/o s none, none ?126 c4 pj[10] pcr[115] option 0 option 1 option 2 option 3 gpio[115] pdi[6] ? ? ?siul pdi ? ? i/o s none, none ?127 c5 pj[11] pcr[116] option 0 option 1 option 2 option 3 gpio[116] pdi[7] ? ? ?siul pdi ? ? i/o s none, none ?128 d5 pj[12] pcr[117] option 0 option 1 option 2 option 3 gpio[117] pdi[8] emiosb[17] ? ?siul pdi pwm/timer ? i/o m1 none, none ?135 c6 pj[13] pcr[118] option 0 option 1 option 2 option 3 gpio[118] pdi[9] emiosb[20] ? ?siul pdi pwm/timer ? i/o m1 none, none ?136 d6 pj[14] pcr[119] option 0 option 1 option 2 option 3 gpio[119] pdi[10] emiosa[20] ? ?siul pdi pwm/timer ? i/o m1 none, none ?137 a7 pj[15] pcr[120] option 0 option 1 option 2 option 3 gpio[120] pdi[11] emiosa[19] ? ?siul pdi pwm/timer ? i/o m1 none, none ?138 b7 pk[0] pcr[121] option 0 option 1 option 2 option 3 gpio[121] pdi[12] emiosa[18] dcu_tag ?siul pdi pwm/timer dcu i/o m1 none, none ?141 c7 table 8. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapbga
pinout and signal descriptions mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 49 pk[1] pcr[122] option 0 option 1 option 2 option 3 gpio[122] pdi[13] emiosa[17] ? ?siul pdi pwm/timer ? i/o m1 none, none ?142 d7 pk[2] pcr[123] option 0 option 1 option 2 option 3 gpio[123] mcko pdi[10] ? ?siul nexus pdi ? i/o f none, none ?33b12 pk[3] pcr[124] option 0 option 1 option 2 option 3 gpio[124] mseo pdi[11] ? ?siul nexus pdi ? i/o m1 none, none ?34c12 pk[4] pcr[125] option 0 option 1 option 2 option 3 gpio[125] evto pdi[12] ? ?siul nexus pdi ? i/o m1 none, none ?35d12 pk[5] pcr[126] option 0 option 1 option 2 option 3 gpio[126] evti pdi[13] ? ?siul nexus pdi ? i/o m1 none, none ?37a11 pk[6] pcr[127] option 0 option 1 option 2 option 3 gpio[127] mdo0 pdi[14] ? ?siul nexus pdi ? i/o m1 none, none ?38b11 pk[7] pcr[128] option 0 option 1 option 2 option 3 gpio[128] mdo1 pdi[15] ? ?siul nexus pdi ? i/o m1 none, none ?40c11 pk[8] pcr[129] option 0 option 1 option 2 option 3 gpio[129] mdo2 pdi[16] ? ?siul nexus pdi ? i/o m1 none, none ?42d11 table 8. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapbga
mpc5606s microcontroller data sheet, rev. 8 pinout and signal descriptions freescale semiconductor 50 pk[9] pcr[130] option 0 option 1 option 2 option 3 gpio[130] mdo3 pdi[17] ? ?siul nexus pdi ? i/o m1 none, none ?44a10 pk[10] pcr[131] option 0 option 1 option 2 option 3 gpio[131] sda_1 emiosa[15] ? ?siul i 2 c_1 pwm/timer ? i/o s none, none ?52 n6 pk[11] pcr[132] option 0 option 1 option 2 option 3 gpio[132] scl_1 emiosa[14] ? ?siul i 2 c_1 pwm/timer ? i/o s none, none ?53 n5 pk[12] ? ? reserved ? ? ? ? ? ? ? ? pk[13] ? ? reserved ? ? ? ? ? ? ? ? pk[14] ? ? reserved ? ? ? ? ? ? ? ? pk[15] ? ? reserved ? ? ? ? ? ? ? ? 1 alternate functions are chosen by setting the values of the pcr[n].pa bitfields inside the siul module. pcr[ n ].pa=00 ? option 0; pcr[ n ].pa=01 ? option 1; pcr[ n ].pa=10 ? option 2; pcr[ n ].pa=11 ? option 3. this is intended to select the output fu nctions; to use one of the input functions, the pcr[ n ].ibe bit must be written to 1, regardless of th e values selected in the pcr[ n ].pa bitfields. for this reason, the value correspondi ng to an input-only function is reported as ?. 2 special functions are enabled independently from the standard digital pin functions. e nabling standard i/o functions in the pcr registers may interfere with their functionality. adc functions are enabled using the pcr[apc] bit; other functions are enabled by enabling the respective module. 3 using the psmi registers in the system integration unit lite (siu l), different pads can be multiplexed to the same peripheral i nput. please see the siul chapter of the mpc5606s microcontroller reference manual for details. 4 see ta bl e 9 . 5 reset configuration is given as i/o direct ion and pull, for example, ?input, pullup?. 6 this option on this pin has alternate functi ons that depend on whether the quadspi is in spi mode or in serial flash mode (sfm) . 7 out of reset, pins ph[0:3] are available as jtag pins (tck, tdi, tdo, and tms, respectively). it is up to the user to configure pins ph[0:3] when needed. 8 this pin can be used for lcd supply pin vlcd. refer to the vo ltage supply pin descriptions in the mpc5606s data sheet for detai ls. table 8. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapbga
pinout and signal descriptions mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 51 table 9. pad type descriptions abbreviation 1 1 the pad descriptions refer to the differen t pad configuration register (pcr) types. chapter 37, system integration unit lite (siul) , for the features available for each pad type. description f fast (with gpio and digital alternate function) j slow pads with analog muxing (built for adc channels) m1 medium (with gpio and digital alternate function) m2 programmable medium/slow pad (programmed via the slew rate control in the pcr): slew rate disabled: slow driver configuration (ac/dc parameters same as for a slow pad) slew rate enabled: medium driver configuratio n (ac/dc parameters same as for a medium pad) s slow (with gpio and digital alternate function) smd stepper motor driver (with slew rate control) x oscillator
mpc5606s microcontroller data sheet, rev. 8 pinout and signal descriptions freescale semiconductor 52 2.9.1 signal details table 10. signal details signal peripheral description abs[0] bam alternate boot se lect. gives an option to boot by downloading code via can or lin. ans[0:15] adc inputs used to bring into th e device sensor-based signals for a/d conversion. ans[0:15] connect to atd channels [32:47]. ma[0:2] adc these three control bits are output to enable the selection for an external analog mux for expansion channels. the available 8 multiplexed channels connect to atd channels [64:71]. fabm force alternate boot mode. forces the device to boot from the external bus (can or lin). if not asserted, the device boots up from the lowest flash sector containing a valid boot signature. dcu_de dcu indicates that valid pixels are present. dcu_hsync dcu horizontal sync pulse for tft-lcd display. dcu_pclk dcu output pixel clock for tft-lcd display. dcu_r[0:7], dcu_g[0:7], dcu_b[0:7] dcu red, green and blue color 8-bit pixel values for tft-lcd displays. dcu_tag dcu indicates when a tagged pixel is present in safety mode. dcu_vsync dcu vertical sync pulse for tft-lcd display. pcs[0..2]_0, pcs[0..2]_1 dspi peripheral chip selects when device is in master mode; not used in slave modes. sck_0, sck_1 dspi spi clock signal?bidirectional. sin_0, sin_1 dspi spi data input signal. sout_0, sout_1 dspi spi data output signal. pcs0_2 quadspi peripheral chip select for serial flash mode or chip select 0 for spi master mode. io2/pcs1_2 quadspi chip select 1 for spi mast er mode and bidirectional io2 for serial flash mode. io3/pcs2_2 quadspi chip select 2 for spi mast er mode and bidirectional io3 for serial flash mode. io0/sin_2 quadspi data input signal for spi master and slave modes and bidirectional io0 for serial flash mode. io1/sout_2 quadspi data output signal for spi master and slave modes and bidirectional io1 for serial flash mode. sck_2 quadspi clock output signal for spi master and serial flash modes and clock input signal for spi slave mode. emiosa[8:23], emiosb[16:23] emios enhanced modular input output system. 16+8 channel emios for timed input or output functions.
pinout and signal descriptions mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 53 canrx_0, canrx_1 flexcan receive (rx) pins for the can bus transceiver. cantx_0, cantx_1 flexcan transmit (tx) pins for the can bus transceiver. scl_0, scl_1, scl_2, scl_3 i 2 c bidirectional serial clock compatible with i 2 c specifications. sda_0, sda_1, sda_2, sda_3 i 2 c bidirectional serial data compatible with i 2 c specifications. tck jtag debug port serial clock as per jtag specifications. tdi jtag debug port serial data input port as per jtag standards specifications. tdo jtag debug port serial data output port as per jtag standards specifications. tms jtag debug port test mode select si gnal for the jtag tap controller state machine and indicates various state transitions for the tap controller in the device. bp[0:3] lcd backplane signals from the lcd controlling the backplane reference voltage for the lcd display. fp[0:39] lcd frontplane signals for lcd segments. evti nexus nexus2+ event input trigger. evto nexus nexus2+ event output trigger. mcko nexus output clock for the development tool. mdo[0:3] nexus message output port pins that send information bits to the development tools for messages such as branch trace message (btm), ownership trace message (otm), data trace message (dtm). only available in reduced port mode. mseo nexus output pin?indicates the start or end of the variable length message on the mdo pins. pdi[0:17] dcu (pdi) video/graphic data in various rgb modes input to the dcu. pdi_de dcu (pdi) input signal indicates the va lidity of pixel data on the input pdi data bus. pdi_hsync dcu (pdi) input indicates the timing re ference for the start of each frame line for the pdi input data. pdi_pclk dcu (pdi) input pixel clock from pdi. pdi_vsync dcu (pdi) input indicates the timing re ference for the start of a frame for the pdi input data. rxd_0 linflex sci/lin receive data signal?this port is used to download the code for the bam boot sequence. table 10. signal details (continued) signal peripheral description
mpc5606s microcontroller data sheet, rev. 8 pinout and signal descriptions freescale semiconductor 54 rxd_1 linflex sci/lin receive data signal . input pad for the lin sci module. connects to the internal lin second port. txd_0 linflex sci/lin transmit data signal. this port is used to download the code for the bam boot sequence. txd_1 linflex sci/lin transmit data signal?t ransmit (output) port for the second lin module in the chip. sound sgl sound signal to the speaker/buzzer. ssd[0:5]_0 ssd[0:5]_1 ssd[0:5]_2 ssd[0:5]_3 ssd bidirectional control of stepper motors using stall detection module. m[0:5]c0m m[0:5]c0p m[0:5]c1m m[0:5]c1p smc controls stepper motors in various configurations. clkout mc_cgm output clock?it can be select ed from several internal clocks of the device from the clock generation module. table 10. signal details (continued) signal peripheral description
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 55 3 electrical characteristics 3.1 introduction this section contains electrical char acteristics of the device as well as temperature and power considerations. this product contains devices to protect the inputs against damage due to high static voltages. however, it is advisable to tak e precautions to avoid application of any voltage higher than the specified maximum rated voltages. to enhance reliability, unused inputs can be driven to an appropriate logic voltage level (v dd or v ss ). this could be done by internal pull up and pull down, which is provided by the product for most general purpose pins. the parameters listed in the following tables represent th e characteristics of the device and its demands on the system. in the tables where the device lo gic provides signals with their respective timing characteristics, the symbol ?cc? for control ler characteristics is included in the symbol column. in the tables where the external system mu st provide signals with their respective timing characteristics to the device, the sy mbol ?sr? for system requirement is included in the symbol column. 3.2 parameter classification the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding, the classifications listed in table 11 are used and the parameters are tagg ed accordingly in the tables where appropriate. note the classification is shown in the column labeled ?c? in the parameter tables where appropriate. 3.3 nvusro register portions of the device configuration, such as high voltage supp ly, oscillator margin, and watch dog enable/disable after reset a re controlled via bit values in the nonvolatile user options (nvusro) register. for a detailed description of the nvusro register, please see the chip reference manual. 3.3.1 nvusro[pad3v5v] field description table 12 shows how nvusro[pad3v5v] controls the device configuration. table 11. parameter classifications classification ta g tag description p those parameters are guaranteed during production testing on each individual device. c those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all values shown in the typical column are within this category. d those parameters are derived mainly from simulations.
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 56 the dc electrical characteristics are dependent on the pad3v5v bit value. 3.3.2 nvusro[oscillator_margin] field description table 12 shows how nvusro[oscillator_margin] controls the device configuration. the 4?16 mhz fast ex ternal crystal oscillator consumption is dependent on the oscillator_margin bit value. 3.4 absolute maximum ratings table 12. pad3v5v field description 1 1 see the device reference manual for more information on the nvusro register. value 2 2 default manufacturing value before flash initialization is ?1? (3.3 v) description 0 high voltage supply is 5.0 v 1 high voltage supply is 3.3 v table 13. oscillator_margin field description 1 1 see the device reference manual for more information on the nvusro register. value 2 2 default manufacturing value before flash initialization is ?1? description 0 low consumption configuration (4 mhz/8 mhz) 1 high margin configuration (4 mhz/16 mhz) table 14. absolute maximum ratings symbol c parameter conditions value unit min max v dda sr c voltage on vdda pin (adc reference) with respect to ground (v ssa ) ? ?0.3 6.0 v v ssa sr c voltage on vssa (adc reference) pin with respect to v ss ?v ss ?0.1 v ss + 0.1 v v ddpll cc c voltage on vddpll (1.2 v pll supply) pin with respect to ground (v sspll ) ? ?0.1 1.4 v v sspll sr c voltage on vsspll pin with respect to v ss12 ?v ss12 ?0.1 v ss12 + 0.1 v v ddr sr c voltage on vddr pin (regulator supply) with respect to ground (v ssr ) ? ?0.3 6.0 v v ssr sr c voltage on vssr (regulator ground) pin with respect to v ss ?v ss ?0.1 v ss + 0.1 v v dd12 cc c voltage on vdd12 pin with respect to ground (v ss12 ) ? ?0.1 1.4 v v ss12 cc c voltage on vss12 pin with respect to v ss ?v ss ?0.1 v ss + 0.1 v v dde_a 1 sr c voltage on vdde_a (i/o supply) pin with respect to ground (v sse_a ) ? ?0.3 6.0 v
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 57 note stresses exceeding the recommended absolute maximum ratings ma y cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indi cated in the operational sections of this specification are not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during overload conditions (v in >v dd or v in mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 58 3.4.1 recommended operating conditions note maximum slew time for the supplies to ramp up should be 1 second, which is the slowest ramp-up time. caution v dde_c and v dda must be the same voltage. v ddmb and v ddmc must be the same voltage. table 15. recommended operating conditions (3.3 v) symbol c parameter conditions value unit min max v dda 1 sr c voltage on vdda pin (adc reference) with respect to ground (v ss ) ?3.03.6v c relative to v dde_c v dd ?0.1 v dd + 0.1 v ssa sr c voltage on vssa (adc re ference) pin with respect to v ss ?v ss ?0.1 v ss + 0.1 v v sspll sr c voltage on vsspll pin with respect to v ss12 ?00v v ddr 2 sr c voltage on vddr pin (regulator supply) with respect to ground (v ssr ) ?3.03.6v v ssr sr c voltage on vssr (regulator groun d) pin with respect to v ss12 ?00v v ss12 4 cc c voltage on vss12 pin with respect to v ss ?v ss ?0.1 v ss + 0.1 v v dd 3,4,5 sr c voltage on vdd pins (vdde_a, vdde_b, vdde_c, vdde_e, vddma, vddmb, vddmc) with respect to ground (v ss ) ?3.03.6v v ss 6 sr c i/o supply ground ? 0 0 v v dde_a sr c voltage on vdde_a (i/o supply) pin with respect to ground (v sse_a ) ?3.03.6v v dde_b sr c voltage on vdde_b (i/o supply) pin with respect to ground (v sse_b ) ?3.03.6v v dde_c sr c voltage on vdde_c (i/o supply) pin with respect to ground (v sse_c ) ?3.03.6v v dde_e sr c voltage on vdde_e (i/o supply) pin with respect to ground (v sse_e ) ?3.03.6v v ddma sr c voltage on vddma (stepper motor supply) pin with respect to ground (v ssma ) ?3.03.6v v ddmb sr c voltage on vddmb (stepper motor supply) pin with respect to ground (v ssmb ) ?3.03.6v v ddmc sr c voltage on vddmc (stepper motor supply) pin with respect to ground (v ssmc ) ?3.03.6v v ssosc sr c voltage on vssosc (oscillator ground) pin with respect to v ss ?00v
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 59 v lcd sr c voltage on vlcd (lcd supply) pin with respect to v ss ?0v dde_a + 0.3 v tv dd sr c v dd slope to ensure correct power up ? 5 ? 10 ?6 0.25 v/s t a sr c ambient temperature under bias ? ?40 105 c t j sr c junction temperature under bias ?40 150 1 100 nf capacitance needs to be provided between v dda /v ssa pair. 2 at least 10 f capacitance must be connected between v ddr and v ssr . this is required because of sharp surge due to external ballast. 3 v dd refers collectively to i/o voltage supplies, i.e., v dde_a , v dde_b , v dde_c , v dde_e , v ddma , v ddmb and v ddmc . 4 100 nf capacitance needs to be provided between each v dd /v ss pair 5 full electrical specification cannot be guaranteed when vo ltage drops below 3.0 v. in particular, adc electrical characteristics and i/o?s dc electrical specification may not be guaranteed. when voltage drops below v lv d h v l device is reset. 6 v ss refers collectively to i/o voltage supply grounds, i.e., v sse_a , v sse_b , v sse_c , v sse_e , v ssma , v ssmb and v ssmc ) unless otherwise noted. table 16. recommended operating conditions (5.0 v) symbol c parameter conditions value unit min max v dda 1 sr c voltage on vdda pin (adc reference) with respect to ground (v ss ) ?4.55.5v c voltage drop 2 3.0 5.5 c relative to v dde_c v dd ?0.1 v dd + 0.1 v ssa sr c voltage on vssa (adc reference) pin with respect v ss ?v ss ?0.1 v ss + 0.1 v v sspll sr c voltage on vsspll pin with respect to v ss12 ?00v v ddr 3 sr c voltage on vddr pin (regulator supply) with respect to ground (v ssr ) ?4.55.5v c voltage drop 2 3.0 5.5 c relative to v dd v dd ?0.1 v dd + 0.1 v ssr sr c voltage on vssr (regulator ground) pin with respect to v ss12 ?00v v ss12 cc c voltage on vss12 pin with respect to v ss ?v ss ?0.1 v ss + 0.1 v v dd 4,5 sr c voltage on vdd pins (vdde_a, vdde_b, vdde_c, vdde_e, vddma, vddmb, vddmc) with respect to ground (v ss ) voltage drop 2 4.5 5.5 v v ss 6 sr c i/o supply ground ? 0 0 v v dde_a sr c voltage on vdde_a (i/o supply) pin with respect to ground (v sse_a ) ?4.55.5v table 15. recommended operating conditions (3.3 v) (continued) symbol c parameter conditions value unit min max
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 60 note ram data retention is guaranteed with v dd12 not below 1.08 v. 3.4.2 connecting power supply pins: what to do and what not to do ?do: ? have all power/ground supplies connected on the board from a strong supply source rather than weak voltage divider sources unless there is ?no i/o activity? in the section ? meet the supply specifications for max / typical operating conditions to guarantee correct operation ? place the decoupling near the supply/gro und pin pair for emi emissions reduction ? route high-noise supply/ground away from sensitive si gnals (for example, adc cha nnels must be away from smd supply/motor pads) v dde_b sr c voltage on vdde_b (i/o supply) pin with respect to ground (v sse_b ) ?4.55.5v v dde_c 7 sr c voltage on vdde_c (i/o supply) pin with respect to ground (v sse_c ) ?4.55.5v v dde_e sr c voltage on vdde_e (i/o supply) pin with respect to ground (v sse_e ) ?4.55.5v v ddma sr c voltage on vddma (stepper motor supply) pin with respect to ground (v ssma ) ?4.55.5v v ddmb sr c voltage on vddmb (stepper motor supply) pin with respect to ground (v ssmb ) ?4.55.5v v ddmc sr c voltage on vddmc (stepper motor supply) pin with respect to ground (v ssmc ) ?4.55.5v v ssosc sr c voltage on vssosc (oscillator ground) pin with respect to v ss ?00v v lcd sr c voltage on vlcd (lcd supply) pin with respect to v ss ?0v dde_a +0.3 v tv dd sr c v dd slope to ensure correct power up ? 3 ? 10 ?6 0.25 v/s t a sr c ambient temperature under bias ? ?40 105 c t j sr c junction temperature under bias ? ?40 150 c 1 100 nf capacitance needs to be provided between v dda /v ssa pair. 2 full functionality cannot be guaranteed when voltage drop s below 4.5 v. in particular, i/o dc and adc electrical characteristics may not be guaranteed below 4.5 v during the voltage drop sequence. 3 10 f capacitance must be connected between v ddr and v ssr . this is required because of sharp surge due to external ballast. 4 v dd refers collectively to i/o voltage supplies, i.e., v dde_a , v dde_b , v dde_c , v dde_e , v ddma , v ddmb and v ddmc . 5 100 nf capacitance needs to be provided between each v dd /v ss pair 6 v ss refers collectively to i/o voltage supply grounds, i.e., v sse_a , v sse_b , v sse_c , v sse_e , v ssma , v ssmb and v ssmc ) unless otherwise noted. 7 v dde_c should be the same as v dda with a 100 mv variation, i.e., v dde_c = v dda ? 100 mv. table 16. recommended operating conditions (5.0 v) (continued) symbol c parameter conditions value unit min max
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 61 ? use star routing for the ballast supply from the vddr supply to avoid ballast startup noise injected to vddr supply of the device ? use lc inductive filtering for adc, osc, and pll supp lies if these are generated from common board regulators ? do not: ? violate injection current limit per i/o or all i/o pins as per specifications ? connect sensitive supplies/ground on noisy supplies/ground (that is, adc, pll, and osc) ? use smd supply for generation of noise free supp ly as these are most noisy lines in the system ? connect different vdd pins (c onnected together inside the device) to different potentials. 3.5 thermal characteristics 3.5.1 general notes for specification s at maximum junction temperature an estimate of the chip junction temperature, t j , can be obtained from equation 1 : t j = t a + (r ? ja ? p d ) eqn. 1 where: t a = ambient temperature for the package (c) r ? ja = junction to ambient th ermal resistance (c/w) p d = power dissipation in the package (w) table 17. lqfp thermal characteristics symbol c parameter conditions value unit 144-pin 176-pin r ? ja cc d thermal resistance, junction-to-ambient natural convection 1 1 junction-to-ambient thermal resistance determined pe r jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. single layer board?1s 50 43 c/w cc four layer board?2s2p 41 35 c/w r ? jma cc d thermal resistance, junction-to-moving-air ambient 2 @ 200 ft./min., single layer board?1s 41 35 c/w cc @ 200 ft./min., four layer board?2s2p 35 30 c/w r ? jb cc d thermal resistance, junction-to-board 2 2 junction-to-board thermal resistance determined pe r jedec jesd51-8. thermal test board meets jedec specification for the specified package. ?2924c/w r ? jctop cc d thermal resistance, junction-to-case (top) 3 3 junction-to-case at the top of the package determi ned using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported va lue includes the thermal resistance of the interface layer. ?109c/w ? jt cc d junction-to-package top thermal characterization parameter, natural convection 4 4 thermal characterization parameter indicating the te mperature difference between the package top and the junction temperature per jedec jesd51-2. when greek le tters are not available, the thermal characterization parameter is written as psi-jt. ?22c/w
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 62 the thermal resistance values used are based on the jedec jesd 51 series of standards to provide consistent values for estimations and comparisons. th e difference between the values determined fo r the single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a grou nd plane (2s2p), demonstrate that the effective thermal resistan ce is not a constant. the therma l resistance depends on the: ? construction of the application board (number of planes) ? effective size of the boar d that cools the component ? quality of the thermal and elect rical connections to the planes ? power dissipated by adjacent components connect all the ground and power balls to the respective planes with one via per ball. using fewer vias to connect the package to the planes reduces the thermal perfor mance. thinner planes also reduce the thermal performance. when the clearance between the vias leave the planes virtually disconnected, the thermal pe rformance is also greatly reduced. as a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. the value obtained on a board with the internal planes is usually within the normal range if the application board has: ? one oz. (35 micron nominal thickness) internal planes ? components are well separated ? overall power dissipation on the board is less than 0.02 w/cm 2 the thermal performance of any component depends on the power dissipation of the surrounding components. in addition, the ambient temperature varies widely within the application. for many natural conv ection and especially cl osed box applications, the board temperature at the perimeter (edge ) of the package is approxim ately the same as the loca l air temperature near the device. specifying the local ambi ent conditions explicitly as th e board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. at a known board temperature, the junction temperature is estimated using equation 2 : t j = t b + (r ? jb ? p d ) eqn. 2 where: t b = board temperature for th e package perimeter (c) r ? jb = junction-to-board thermal resistance (c/w) per jesd51-8s p d = power dissipation in the package (w) when the heat loss from the package case to the air does not factor in to the calculation, an accep table value for the junction temperature is predictable. ensure the appl ication board is similar to the thermal te st condition, with the component soldered to a board with internal planes. the thermal resistance is expressed as the sum of a junctio n-to-case thermal resistance pl us a case-to-ambient thermal resistance: r ? ja = r ? jc + r ? ca eqn. 3 where: r ? ja = junction to ambient thermal resistance (c/w) r ? jc = junction to case thermal resistance (c/w) r ? ca = case to ambient thermal resistance (c/w) r ? jc s device related and is not affected by other factors. the thermal environment can be controlled to change the case-to-ambient thermal resistance, r ? ca . for example, change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. this description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient. for most pack ages, a better model is required.
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 63 a more accurate two-resistor thermal model can be construc ted from the junction-to-board thermal resistance and the junction-to-case thermal resistance. the junction-to-case thermal resistance descri bes when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. the junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the pr inted circuit board. this model can be used to generate simple estimations and for computational fluid dynamics (cfd) thermal models. to determine the junction temperature of th e device in the application on a prototyp e board, use the thermal characterization parameter ( ? jt ) to determine the junction temperature by measuring the temperature at the top cente r of the package case using equation 4 : t j = t t + ( ? jt x p d ) eqn. 4 where: t t = thermocouple temperature on top of the package (c) ? jt = thermal characterization parameter (c/w) p d = power dissipation in the package (w) the thermal characterization parameter is measured in compli ance with the jesd51-2 specificat ion using a 40-gauge type t thermocouple epoxied to the top center of the package case. positio n the thermocouple so that the thermocouple junction rests on the package. place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction. place the thermocoup le wire flat against the package case to avoi d measurement errors caused by the cooling effects of the thermocouple wire. references: semiconductor equipment and materials international 805 east middlefield rd. mountain view, ca 94043 usa (415) 964-5111 mil-spec and eia/jesd (jedec) specifi cations are available from global engi neering documents at 800-854-7179 or 303-397-7956. jedec specifications are available on the web at http://www.jedec.org . 3.6 electromagnetic compatib ility (emc) characteristics susceptibility tests are performed on a sa mple basis during produ ct characterization. 3.6.1 emc requirements on board the following practices help minimize noise in applications. ? place a 100 nf capacitor between each of the v dd12 /v ss12 supply pairs and also between the v ddpll /v sspll pair. the voltage regulator also requires stab ility capacitors for these supply pairs. ? place a 10 f capacitor on vddr. ? isolate vddr with ballast emitter to avoi d voltage droop during standby mode exit. ? enable pad slew rate only as n ecessary to eliminate i/o noise: ? enabling slew rate for smd pads will reduce noise on motors. ? disabling slew rate for non-smd pads will reduce noise on non-smd i/os. ? enable pll modulation ( 2%) for system clock. ? place decoupling capacitors for all hv supplies close to the pins.
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 64 3.6.2 designing hardened software to avoid noise problems emc characterization and optimiza tion are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user apply emc software optimization and prequalification tests in relation with the emc level requested for his application. ? software recommendations ? the softwa re flowchart must include the manage ment of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) ? prequalification trials ? most of the common failures ( unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device. when unexpected behavior is detected, the software can be hardened to prev ent unrecoverable errors occurring. 3.6.3 electromagnetic interference (emi) 3.6.4 absolute maximum ratings (electrical sensitivity) based on two different tests (esd and lu) using specific measurement me thods, the product is stressed in order to determine its performance in terms of electrical sensitivity. 3.6.4.1 electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) ar e applied to the pins of each sample accord ing to each pin combination. the sample size de pends on the number of suppl y pins in the device (3 pa rts*(n+1) suppl y pin). this test conforms to the aec- q100-002/-003/-011 standard. table 18. emi testing specifications 1 1 emi testing and i/o port waveforms per sae j1752/3 issued 1995-03. symbol c parameter conditions value unit min typ max ? sr t scan range 150 khz ? 30 mhz: rbw 9 khz, step size 5 khz 30 mhz ? 1 ghz: rbw 120 khz, step size 80 khz 0.15 ? 1000 mhz ? sr t operating frequency crystal frequency 8 mhz ? 64 ? mhz ?srtv dd12 , v ddpll operating voltages ? ? 1.28 ? v ? sr t vdd, vdda operating voltages ??5?v ? sr t maximum amplitude no pll frequency modulation ? 33 ? dbv 2% pll frequency modulation ? 30 ? ? sr t operating temperature ??25?c
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 65 3.6.4.2 static latch-up (lu) two complementary static tests are required on six parts to assess the latch-up performance: ? a supply overvoltage is appl ied to each power supply pin. ? a current injection is applied to each input, output and configurable i/o pin. these tests are compliant with the eia/jesd 78 ic latch-up standard. 3.7 power management electrical characteristics 3.7.1 voltage regulator electrical characteristics the internal high power or main regulator (hpreg) requires an external npn ballast transistor (see table 21 and table 22 ) to be connected as shown in figure 7 as well as an external capacitance (c reg ) to be connected to the device in order to provide a stable low voltage digital supp ly to the device. capacitances should be placed on the board as near as possible to the associ ated pins. care should also be taken to limit the serial inductance of the board to less than 15 nh. for the mpc5606s microcontroller, 100 nf should be placed between each of the v dd12 /v ss12 supply pairs and also between the v ddpll /v sspll pair. these decoupling capacitors are in addition to the required stability capacitance. additionally, 10 f should be placed between the v ddr pin and the adjacent v ss pin. v ddr = 3.0 v to 3.6 v / 4.5 v to 5.5 v, t a = ? 40 to 105 c, unless otherwise specified. table 19. esd absolute maximum ratings 1 2 1 all esd testing is in conformity with cdf-aec-q100 stre ss test qualification for au tomotive grade integrated circuits. 2 a device will be defined as a failure if after exposure to esd pulses the device no longer meets the device specification requirements. complete dc parametric and f unctional testing shall be performed per applicable device specification at room temperature followed by ho t temperature, unless specified otherwise in the device specification. symbol c ratings conditions class max value unit v esd(hbm) cc t electrostatic discharge voltage (human body model) t a = 25 c conforming to aec-q100-002 h1c 2000 v v esd(mm) cc t electrostatic discharge voltage (machine model) t a = 25 c conforming to aec-q100-003 m2 200 v esd(cdm) cc t electrostatic discharge voltage (charged device model) t a = 25 c conforming to aec-q100-011 c3a 500 750 (corners) table 20. latch-up results symbol c parameter conditions class lu cc t static latch-up class t a = 105 c conforming to jesd 78 ii level a
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 66 a figure 7. external npn ballast connections the capacitor values listed in table 22 include a de-rating factor of 40%, covering tolerance, te mperature, and aging effects. these factors are taken into account to assure proper ope ration under worst-case conditio ns. x7r type materials are recommended for all capacitors, based on esr characteristics. large capacitors are for re gulator stability and should be lo cated near the external ballast tr ansistor. the number of capacito rs is not important ? only the overall capacitance va lue and the overall esr value are important. small capacitors are for power s upply decoupling, although they do contribute to the overall capacitance values. they should be located close to the device pin. table 21. allowed ballast components part manufacturer recommended derivative bcp68 on, ifx, nxp, fairchild, st, etc. bcp68 bcx68 ifx bcx68-10 bcx68-16 bc817 on, ifx, nxp, fairchild, etc. bc817su bc817-25 bcp56 on, ifx, nxp, fairchild, st, etc. bcp68-10 bcp68-16 2sd1000 nec 2sd1000-ll 2sd1000-lk table 22. ballast component parameters parameter specification capacitance on vddr 10 ? f (minimum) place close to npn collector stability capacitance on vdd12 40 ? f (minimum) place close to npn emitter decoupling capacitance on vdd12 100 nf ? number of pins (minimum) place on each vdd12/vss12 pair and on the pll supply/ground pair base resistor 20 k ? vrc_ctrl v ddr v dd12 20 k ?
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 67 table 23. voltage regulator electrical characteristics symbol c parameter conditions value unit min typ max t j sr c junction temperature ? ?40 ? 150 c i reg cc c current consumption reference included, @ 55 c no load @ full load ?? 2 11 ma i l cc c output current capacity dc load current ? ? 200 ma v dd12 cc c output voltage pre-trimming sigma <7mv ? 1.330 ? v p post-trimming 1.15 1.28 ? v sr c external decoupling/stability capacitor 4 capacitances of 10 f each ??10 ? 4f c esr of external cap 0.05 ? 0.2 ? c 1 bond wire r + 1 pad r 0.2 1 ? l bond cc d bonding inductance for bipolar base control pad ? 0 ? 15 nh cc d power supply rejection @ dc @ no load c l =10f ? 4 ? ? ?30 db d @ 200 khz @ no load ?100 d @ dc @ 200 ma ?30 d @ 200 khz @ 200 ma ?30 cc d load current transient c l =10f ? 4 ? ? 10% to 90% of i l (max) in 100 ns t su cc c start-up time after input supply stabilizes 1 1 time after the input supply to the voltage regulator has ramped up (v ddr ). c l =10f ? 4 ? ? 100 s
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 68 figure 8. voltage regulator capacitance connection table 24. low-power voltage regulator electrical characteristics symbol c parameter conditions value unit min typ max t j sr c junction temperature ? ?40 ? 150 c i reg cc c current consumption reference included, @ 55 c no load @ full load ?? 5 600 ? a i l cc c output current capacity 1 dc load current ? ? 15 ma v dd12 cc c output voltage pre-trimming sigma <7mv ?1.33?v p post-trimming 1.15 1.24 ? v sr c external decoupling/stabilit y capacitor 4 capacitances of 10 f each 10 ? 4?10 ? 4f c esr of external cap 0.1 ? 0.6 ohm c 1 bond wire r + 1 pad r 0.2 ? 1 ohm l bond cc d bonding inductance for bipolar base control pad ? 0 ? 15 nh 20 kb pd0 (always on domain) pd1 (switchable domain) hpreg ulpreg hpvdd lpvdd off chip npn driver 40 f sw1 (1 ? ) vddr vssr vdd12 vdd12 vddpll vss12 vss12 (c reg n ) chip boundary 10 f (4 10 f) vsspll vdd12 vss12 split sw20 (20 ? ) 20 kb split ulpvdd sw20 ctrl 4kb ctrl 4kb (20 ? ) 20 k ? pd0 logic
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 69 3.7.2 voltage monitor electrical characteristics the device implements a power-on reset (por) module to ensure correct power-up initia lization, as well as four low voltage detectors (lvds) to monitor the v dd and the v dd12 voltage while device is supplied: ? por monitors v dd during the power-up phase to ensure devi ce is maintained in a safe reset state ? lvdhv3 monitors v dd to ensure device reset below minimum functional supply cc d power supply rejection @ dc @ no load c l =10f ? 4??55db d any frequency @ no load 32 d @ dc @ max load 24 d any frequency @ max load 12 cc d load current transient c l =10f ? 4 ? ? 10% to 90% of i l in 10 ? s t su cc c start-up time after input supply stabilizes 2 c l =10f ? 4??700s 1 on this device, the ultra-low-power regulator is always enabled when the low-power regulator is enabled. therefore, the total low-power current capacity is the sum of i l values for the two regulators. 2 time after the input supply to the voltage regulator has ramped up (v ddr ) and the voltage regulator has asserted the power ok signal. table 25. ultra-low-power voltage regulator electrical characteristics symbol c parameter conditions value unit min typ max t j sr c junction temperature ? ?40 ? 150 c i reg cc c current consumption reference included, @ 55 c no load @ full load ?? 2 100 ? a i l cc c output current capacity dc load current ? ? 5 ma v dd12 cc c output voltage (value @ i l = 0 @ 27 c) pre-trimming sigma <7mv ?1.33 ? v post-trimming 1.15 1.24 ? cc d power supply rejection @ dc @ no load ? ? ? 25 db d any frequency @ no load 7 d @ dc @ max load 25 d any frequency @ max load 8 cc d load current transient ? ? ? 10 to 90 ? a in 70 ? s table 24. low-power voltage regulator electrical characteristics (continued) symbol c parameter conditions value unit min typ max
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 70 ? lvdhv5 monitors v dd when application uses device in the 5.0 v 10% range ? lvdlvcor monitors power domain no. 1 ? lvdlvbkp monitors power domain no. 0 figure 9. low voltage monitor vs. reset 3.7.3 low voltage domain power consumption table 27 provides dc electrical characteristic s for significant application modes. th ese values are indi cative values; actual consumption depends on the application. table 26. low voltage monitor electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ?40 to 105 c, unless otherwise specified. value unit min typ max v porh cc p power-on reset threshold ? 1.5 ? 2.6 v v lv d h v 3 h cc p lvdhv3 low voltage detector high threshold ? ? ? 2.9 v v lv d h v 5 h cc p lvdhv5 low voltage detector high threshold ? ? ? 4.4 v v lv d h v 3 l cc p lvdhv3 low voltage detector low threshold ? 2.6 ? ? v v lv d h v 5 l cc p lvdhv5 low voltage detector low threshold ? 3.8 ? ? v v lv d lv c o r h 2 2 l vdlvbkp has same post-tri m thresholds as lvd lv c o r . cc p lvdlvcor low voltage detector high threshold t a = 25 c, after trimming ? ? 1.15 v v lv d lv c o r l cc p lvdlvcor low voltage detector low threshold 1.08 ? ? v v dd v lvdhvxh reset v lvdhvxl
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 71 table 27. dc electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ?40 to 105 c t a value unit min typ max i ddrun 2 2 value is for maximum peripherals turned on. may vary significantly based on different configurations, active peripherals, operating frequency, etc. cc p run mode current ? ? 130 180 ma i ddhalt cc p halt mode current ? ? 4 25 ma i ddstop cc p stop mode current 16 mhz fast internal rc oscillator off, hpvreg off 25c ? 250 1800 ? a 105c ? 5 20 ma 16 mhz fast internal rc oscillator off, hpvreg on 25c ? 2.5 6.5 ma 105c ? 7 25 ma i ddstdby cc c standby mode current see ta b l e 2 8 i ddstdby1 3 3 ulpreg on, hp/lpvreg off, 8 kb ram on, device confi gured for minimum consumption, all possible modules switched off. cc p standby1 mode current 25c ? 20 100 ? a 105c ? 180 ? ? a t j = 150c ? ? 350 1500 ? a i ddstdby2 4 4 ulpreg on, hp/lpvreg off, 32 kb ram on, device conf igured for minimum consumption, all possible modules switched off. cc p standby2 mode current 25c ? 30 100 ? a 105c ? 350 ? ? a t j = 150c ? ? 600 2500 ? a table 28. iddstdby specification 1 1 all current values are typical values. temperature (t a ,c) firc off, 8kb ram on firc on, 8 kb ram on 32 khz sxosc on, 8 kb ram on 32 khz sxosc on, all ram on 3.3v 5.5v 3.3v 5.5v 3.3v 5.5v 3.3v 5.5v ?40 16 ? a25 ? a326 ? a340 ? a16 ? a26 ? a22 ? a32 ? a 018 ? a29 ? a334 ? a347 ? a19 ? a29 ? a26 ? a37 ? a 25 23 ? a33 ? a342 ? a355 ? a24 ? a34 ? a34 ? a45 ? a 55 41 ? a51 ? a363 ? a377 ? a42 ? a53 ? a69 ? a80 ? a 85 93 ? a 104 ? a421 ? a435 ? a100 ? a110 ? a 182 ? a 195 ? a 105 173 ? a 185 ? a502 ? a517 ? a181 ? a194 ? a 344 ? a 358 ? a 125 2 2 values provided for reference only. the permitted temp erature range of the chip is specified separately. 320 ? a 334 ? a648 ? a667 ? a321 ? a335 ? a 620 ? a 638 ? a 150 2 681 ? a 698 ? a 1005 ? a 1028 ? a654 ? a677 ? a1270 ? a1300 ? a
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 72 3.7.4 recommended power-up and power-down order figure 10 shows the recommended order for powering up the power supplies on this device. the 1.2 v regulator output starts after the device?s internal por (vddreg hv) is deasserted at approximately 2.7 v on vddreg. figure 10. recommended order for powering up the power supplies caution the voltages v a and v b in figure 10 must always obey the relation v b ? v a ?0.7v. otherwise, currents from the 1.2 v supply to the 3.3 v supply may result. figure 11 shows the recommended order for powering down the power supplies on this device. it is acceptable for the vdd io hv supply to ramp down faster than the 1.2 v regulator output, even if the latter takes time to discharge the high 40 f capacitance. (the capacitor will ultimately discharge.) vddreg hv supply vddreg hv por (internal) 1.2 v regulator output soft startup (approx. 200 ? s) vdd io hv supply (3?5.5 v) ? 2.7 v ? 200 s v a v b
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 73 figure 11. recommended order for powering down the power supplies caution the vdd io hv supply must be disabled after the vddreg hv supply voltage drops below 1.5 v. this is to ensure that the 1.2 v regulator shuts down before the 3.3 v regulator shuts down. 3.7.5 power-up inrush current profile figure 12 shows the power up inrush current profile of the ballast transistor under the worst possible startup condition (fastest pvt and fastest power ramp time). figure 12. power-up inrush current profile vddreg hv supply ? 2.7 v vddreg hv por (internal) 1.2 v regulator output soft startup (approx. 200 ? s) vdd io hv supply (3?5.5 v) > 1.5 v time to discharge 40 ? f capacitance depends on load 1.2 v supply base control current profile 3?5.5 v
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 74 the hpreg has a ?soft startup? profile that increases the supply in step s of approximately 50 mv in a series of approximately 25 steps. therefore, the peak current is within 750 ma of the maximum current during startup. this eliminates any noise on the vddr supply during startup and charging of npn emitter stability capacita nce of 40 f (minimum). soft startup also occurs when waking up from standby mode to limit noise on the vddr supply. in case vddr is shared between the device and the ballast, it must be star routed on th e board or isolated as much as possible to avoid any noise injected by the ballast. soft startup will he lp to limit this noise but a vddr capacitor close to the ballas t pin is critical here. a minimum cap acitance of 10 f is needed. table 29 shows the typical and maximum startup currents. 3.7.6 hpreg load regulation characteristics the hpreg exhibits a very strong load-regul ation behavior (the transition from low- to high-current state is regulated quickly) . this is illustrated in figure 14 , which shows a 10?150 ma jump over 10 ns. under any case of load transition, the hpreg responds within 100 ns and stabilizes within 5 s. this helps improve the stability of the 1.2 v supply and settling time. figure 13. hpreg load regulation 3.8 i/o pad electrical characteristics 3.8.1 i/o pad types the device provides five main i/o pad types: ? slow pads ? these are the most common pads, providing a good compromise between transition time and low electromagnetic emission. ? medium pads ? these are provided in two types (m1 and m2) and provide transitions fast enough for the serial communication channels. m2 pads include slew rate control. table 29. startup current symbol c parameter value unit typ max i start cc t startup current 300 800 ma 1.2 v supply base control 3 v input supply load
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 75 ? fast pads ? these provide maximum speed. there are used for improved nexus debugging capability. ? smd pads ? these provide additional current capability to drive stepper motor loads. ? digital i/o with analog (j) pad ? these provide input and output digital features and analog input for adc. m2 and fast pads can disable slew rate to reduce electro magnetic emission, at the cost of reducing ac performance. 3.8.2 i/o input dc characteristics table 30 provides input dc electrical ch aracteristics as described in figure 14 . figure 14. i/o input dc electrical characteristics definition table 30. i/o input dc electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v ? 10% / 5.0 v ? 10%, t a = ?40 to 105 c. value unit min typ max v ih sr p input high level cmos schmitt trigger ? 0.65v dd ?v dd + 0.3 v v il sr p input low level cmos schmitt trigger ? ?0.3 ? 0.35v dd v hys cc d input hysteresis cmos schmitt trigger ? 0.1v dd ?? i lkg cc p input leakage current ? ?1 ? 1 ? a t a = ?40c ? 2 ? na t a = 25c ? 2 ? na ct a = 105c ? 12 500 na pt j = 150c ? 70 1000 na r on cc d resistance of the anal og switch inside the j pad type 2 2 applies to the j pad type only. supply range 3.3?5 v ?? 1k ? v il v in v ih pdi = ?1? v dd v hys (gpdi register of siu) pdi = ?0?
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 76 3.8.3 i/o output dc characteristics the following tables provide dc char acteristics for bidirectional pads: ? table 31 provides weak pull figures. both pull- up and pull-down resistances are supported. ? table 32 provides output driver char acteristics for i/o pads wh en in slow configuration. ? table 33 provides output driver characterist ics for i/o pads when in medium configuration (applies to both m1 and m2 type pads). ? table 34 provides output driver char acteristics for i/o pads wh en in fast configuration. ? table 35 provides smd pad characteristics. table 31. i/o pull-up/pull-down dc electrical characteristics 1 1 the pull currents are dependent on the hve settings. symbol c parameter conditions 2 2 v dd = 3.3 v ? 10% / 5.0 v ? 10%, t a = ?40 to 125 c, unless otherwise specified. value unit min typ max |i w- pu | c c p weak pull-up current absolute value v in = v il , v dd = 5.0v ? 10% pad3v5v = 0 10 ? 150 a c pad3v5v = 1 3 3 the configuration pad3v5 = 1 when v dd = 5 v is only a transient configuration during power-up. all pads but reset and nexus output (mdox, evto, mcko) are configured in input or in high impedance state. 10 ? 250 pv in = v il , v dd = 3.3v ? 10% pad3v5v = 1 10 ? 150 |i w- pd | c c p weak pull-down current absolute value v in = v il , v dd = 5.0v ? 10% pad3v5v = 0 10 ? 150 a c pad3v5v = 1 10 ? 250 pv in = v il , v dd = 3.3v ? 10% pad3v5v = 1 10 ? 150 table 32. slow configuration output buffer electrical characteristics symbol c parameter conditions 1 value unit min typ max v oh cc p output high level slow configuration push pull, i oh = ?2 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) 0.8v dd ?? v d push pull, i oh = ?2 ma, v dd = 5.0 v 10%, pad3v5v = 1 2 0.8v dd ?? c push pull, i oh = ?1 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) v dd ?0.8 ? ? v ol cc p output low level slow configuration push pull, i ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ? ? 0.1v dd v d push pull, i ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 1 2 ? ? 0.1v dd c push pull, i ol = 1 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 77 t tr cc t output transition time output pin 3 slow configuration c l = 25 pf, v dd = 5.0 v 10%, pad3v5v = 0 ? ? 50 ns tc l = 50 pf, v dd = 5.0 v 10%, pad3v5v = 0 ??100 tc l = 100 pf, v dd = 5.0 v 10%, pad3v5v = 0 ??125 tc l = 25 pf, v dd = 3.3 v 10%, pad3v5v = 1 ??40 tc l = 50 pf, v dd = 3.3 v 10%, pad3v5v = 1 ??50 tc l = 100 pf, v dd = 3.3 v 10%, pad3v5v = 1 ??75 ? i tr50 cc d current slew at c l = 50 pf slow configuration recommended configuration at v dd = 5.0 v 10%, pad3v5v = 0 v dd = 3.3 v 10%, pad3v5v = 1 ?? 2ma/ns dv dd = 5.0 v 10%, pad3v5v = 1 ? ? 7 1 v dd = 3.3 v ? 10% / 5.0 v ? 10%, t a = ?40 to 105 c, unless otherwise specified 2 this is a transient c onfiguration during powe r-up. all pads but reset and nexus output (mdox, evto, mck) are configured in input or in high impedance state. 3 c l calculation should include device and package capacitances (c pkg < 5 pf). table 33. medium configuration output buffer electrical characteristics symbol c parameter conditions 1 value unit min typ max v oh cc p output high level medium configuration push pull, i oh = ?2 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) 0.8v dd ?? v d push pull, i oh = ?1 ma, v dd = 5.0 v 10%, pad3v5v = 1 2 0.8v dd ?? c push pull, i oh = ?1 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) v dd ?0.8 ? ? v ol cc p output low level medium configuration push pull, i ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ? ? 0.1v dd v d push pull, i ol = 1 ma, v dd = 5.0 v 10%, pad3v5v = 1 2 ? ? 0.1v dd c push pull, i ol = 1 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5 table 32. slow configuration output buffer electrical characteristics (continued) symbol c parameter conditions 1 value unit min typ max
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 78 t tr cc t output transition time out- put pin 3 medium configuration c l = 25 pf, v dd = 5.0 v 10%, pad3v5v = 0 ? ? 10 ns tc l = 50 pf, v dd = 5.0 v 10%, pad3v5v = 0 ??20 tc l = 100 pf, v dd = 5.0 v 10%, pad3v5v = 0 ??40 tc l = 25 pf, v dd = 3.3 v 10%, pad3v5v = 1 ??12 tc l = 50 pf, v dd = 3.3 v 10%, pad3v5v = 1 ??25 tc l = 100 pf, v dd = 3.3 v 10%, pad3v5v = 1 ??40 ? i tr50 cc d current slew at c l = 50 pf medium configuration recommended configuration at v dd = 5.0 v 10%, pad3v5v = 0 v dd = 3.3 v 10%, pad3v5v = 1 ??7ma/ns dv dd = 5.0 v 10%, pad3v5v = 1 ? ? 16 1 v dd = 3.3 v 10% / 5.0 v ? 10%, t a = ?40 to 105 c, unless otherwise specified 2 this is a transient c onfiguration during powe r-up. all pads but reset and nexus output (mdox, evto, mck) are configured in input or in high impedance state. 3 c l includes device and package capacitance (c pkg <5 pf). table 34. fast configuration output buffer electrical characteristics symbol c parameter conditions 1 value unit min typ max v oh cc p output high level fast configuration push pull, i oh = ?14 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) 0.8v dd ?? v d push pull, i oh = ?7 ma, v dd = 5.0 v 10%, pad3v5v = 1 2 0.8v dd ?? c push pull, i oh = ?11 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) v dd ?0.8 ? ? v ol cc p output low level fast configuration push pull, i ol = 14 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ? ? 0.1v dd v d push pull, i ol = 7 ma, v dd = 5.0 v 10%, pad3v5v = 1 2 ? ? 0.1v dd c push pull, i ol = 11 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5 table 33. medium configuration output buff er electrical characteristics (continued) symbol c parameter conditions 1 value unit min typ max
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 79 t tr cc t output transition time output pin 3 fast configuration c l = 25 pf, v dd = 5.0 v 10%, pad3v5v = 0 ?? 4 ns tc l = 50 pf, v dd = 5.0 v 10%, pad3v5v = 0 ?? 6 tc l = 100 pf, v dd = 5.0 v 10%, pad3v5v = 0 ??12 tc l = 25 pf, v dd = 3.3 v 10%, pad3v5v = 1 ?? 4 tc l = 50 pf, v dd = 3.3 v 10%, pad3v5v = 1 ?? 7 tc l = 100 pf, v dd = 3.3 v 10%, pad3v5v = 1 ??12 ? i tr50 cc d current slew at c l = 50 pf fast configuration v dd = 5.0 v 10%, pad3v5v = 0 (recommended configuration) ??55ma/ns dv dd = 3.3 v 10%, pad3v5v = 1 (recommended configuration) ??40 dv dd = 5.0 v 10%, pad3v5v = 1 ? ? 100 1 v dd = 3.3 v ? 10% / 5.0 v ? 10%, t a = ?40 to 105 c, unless otherwise specified 2 this is a transient c onfiguration during powe r-up. all pads but reset and nexus output (mdox, evto, mck) are configured in input or in high impedance state. 3 c l includes device and package capacitance (c pkg <5 pf). table 35. smd pad electrical characteristics symbol c parameter conditions value unit min typ max v il cc p low level input voltage ? ?0.4 ? 0.35 ? v ddm v v ih cc p high level input voltage ? 0.65 ? v ddm ?v ddm +0.4 v hyst cc c schmitt trigger hysteresis ? 0.1 ? v ddm ?? v ol cc p low level output voltage i ol = 20 ma 1 ? ? 0.32 i ol = 30 ma 2 ? ? 0.48 v oh cc p high level output voltage i oh = ?20 ma 1 v ddm ?0.32 ? ? i oh = ?30 ma 2 v ddm ?0.48 ? ? table 34. fast configuration output buffer electrical characteristics (continued) symbol c parameter conditions 1 value unit min typ max
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 80 3.8.4 i/o pad current specification the i/o pads are distributed across the i/o supply segm ent. each i/o supply segm ent is associated to a v dd /v ss supply pair as described in table 36 . table 37 provides i/o consumption figures. in order to ensure device reliability, the average current of the i/o on a si ngle segment should remain below the i av g s e g maximum value. in order to ensure device functionality, the sum of the dynamic and static current of the i/o on a single segment should remain below the i dynseg maximum value. i pu cc p internal pull-up device current v in =v il ?130 ? ? ? a v in =v ih ? ? ?10 i pd cc p internal pull-down device current v in =v il 10 ? ? v in =v ih ? ? 130 i in cc p input leakage current ? ?1 ? 1 r dsonh cc c smd pad driver active high impedance i oh ? ?30 ma 2 ??16 ? r dsonl cc c smd pad driver active low impedance i ol ? 30 ma 2 ??16 ? v omatch cc c output driver matching v oh /v ol i oh /i ol ? 30 ma 2 ??90mv 1 vdd = 5.0 v 10%, tj = ?40 to 150 c. 2 vdd = 5.0 v 10%, tj = ?40 to 130 c. table 36. i/o supply segment package supply segment a 1 1 lcd pad segment containing pad supplies v dde_a b 2 2 miscellaneous pad segment containing pad supplies v dde_b c 3,4 3 adc pad segment containing pad supplies v dde_c 4 v dde_c should be the same as v dda with a 100 mv variation, i.e., v dde_c = v dda ? 100 mv. d 5 5 stepper motor pad segment containing i/o supplies v ddma , v ddmb , v ddmc e 6 6 miscellaneous pad segment containing pad supplies v dde_e 144 lqfp pins 1?21 pins 113?144 pins 22? 52 pins 53?72 pins 73?102 pins 103?112 176 lqfp pins 1?21 pins 143?176 pins 22?68 pins 69?88 pins 89?118 pins 119?142 table 35. smd pad electrical characteristics (continued) symbol c parameter conditions value unit min typ max
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 81 table 37. i/o consumption symbol c parameter conditions 1 value unit min typ max i swtslw cc d dynamic i/o current for slow configuration c l = 25 pf, v dd = 5.0 v 10%, pad3v5v = 0 ??20ma dc l = 25 pf, v dd = 3.3 v 10%, pad3v5v = 1 ??16 i swtmed cc d dynamic i/o cu rrent for medium configuration c l = 25 pf, v dd = 5.0 v 10%, pad3v5v = 0 ??29ma dc l = 25 pf, v dd = 3.3 v 10%, pad3v5v = 1 ??17 i swtfst cc d dynamic i/o current for fast configuration c l = 25 pf, v dd = 5.0 v 10%, pad3v5v = 0 ??110ma dc l = 25 pf, v dd = 3.3 v 10%, pad3v5v = 1 ??50 i rmsslw cc d root mean square i/o current for slow configuration c l = 25 pf, 2 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??2.3ma dc l = 25 pf, 4 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??3.2 dc l = 100 pf, 2 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??6.6 dc l = 25 pf, 2 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??1.6 dc l = 25 pf, 4 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??2.3 dc l = 100 pf, 2 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??4.7 i rmsmed cc d root mean square i/o current for medium configuration c l = 25 pf, 2 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??6.6ma dc l = 25 pf, 4 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??13.4 dc l = 100 pf, 2 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??18.3 dc l = 25 pf, 2 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??5.0 dc l = 25 pf, 4 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??8.5 dc l = 100 pf, 2 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??11.0
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 82 3.9 ssd specifications 3.9.1 electrical characteristics i rmsfst cc d root mean square i/o current for fast configuration c l = 25 pf, 2 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??22.0ma dc l = 25 pf, 4 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??33.0 dc l = 100 pf, 2 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??56.0 dc l = 25 pf, 2 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??14.0 dc l = 25 pf, 4 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??20.0 dc l = 100 pf, 2 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??25.0 i dynseg sr d sum of all the dynamic and static i/o current within a supply seg- ment v dd = 5.0 v 10%, pad3v5v = 0 ? ? 110 ma dv dd = 3.3 v 10%, pad3v5v = 1 ? ? 65 i avgseg sr d sum of all the static i/o current within a supply segment v dd = 5.0 v 10%, pad3v5v = 0 ? ? 70 ma dv dd = 3.3 v 10%, pad3v5v = 1 ? ? 65 i ddmxavg sr d sum of currents of two motors assigned to segment v ddmx , v ssmx pair v dd = 5.0 v 10%, pad3v5v = 0 t j =130 ? c ??90 v dd = 5.0 v 10%, pad3v5v = 0 t j =?40 ? c ??120 1 v dd = 3.3 v ? 10% / 5.0 v ? 10%, t a = ?40 to 105 c, unless otherwise specified table 38. ssd electrical characteristics symbol c parameter value 1 unit min typ max v vref cc p reference voltage (i vref =0) v ddm /2?0.03 v ddm /2 v ddm /2 + 0.03 v i vref cc p reference voltage output current 1.85 ? ? ma r in cc d input resistance (against v ddm /2) 0.8 1.0 1.2 m ? v in cc c input common mode range v ssm ?v ddm v ssd const cc c ssd constant 0.549 0.572 0.597 ? table 37. i/o consumption (continued) symbol c parameter conditions 1 value unit min typ max
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 83 3.9.2 accumulator values equation 5 describes the accumulator value in unipolar configuration. the voltage v in is applied between the integrator input and v ddm . the internal generated referen ce voltage is not connected. the accu mulator value is a function of v ddm , the number of samples (nsample) taken and the ssd cons tant (ssdconst). the ssd constant and of fset (ssdconst, ssdoffset) vary with temperature and process. eqn. 5 equation 6 describes the accumulator value in bipolar configuration. the voltage v in is applied between the integrator input and the reference output. the accumulator value depends on the same parameters as in the unipolar case but the inaccuracy of the voltage reference (vvref) is compensated. eqn. 6 3.10 reset electrical characteristics the device implements a dedi cated bidirectional reset pin. ssd offset cc c ssd offset (unipolar, n sample = 256) ?9 ? 9 counts ssd offset (bipolar, n sample = 256) ?8 ? 8 ssd offset (bipolar with offset cancellation, n sample = 256) ?5 ? 5 f ssdsmp cc d ssd cmpout sample rate 0.5 ? 2.0 mhz 1 vdd = 5.0v ? 10%, tj = ?40 to +150 c. table 38. ssd electrical characteristics (continued) symbol c parameter value 1 unit min typ max accval v in vddm ?? 2 ? ? vddm ssdconst ? ---------------------------- ------------------- - nsample ssdoffset + ? = accval v in vddm ssdconst ? ---------------------------- ------------------- - nsample ssdoffset + ? =
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 84 figure 15. start-up reset requirements figure 16. noise filtering on reset signal v il v dd device reset forced by reset v ddmin v ih device start-up phase v reset v reset v il v ih v dd filtered by hysteresis filtered by lowpass filter w frst w nfrst hw_rst ?1? ?0? filtered by lowpass filter w frst unknown reset state device under hardware reset
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 85 table 39. reset electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ?40 to 105 c, unless otherwise specified value unit min typ max v ih sr p input high level cmos schmitt trigger ?0.65v dd ?v dd + 0.4 v v il sr p input low level cmos schmitt trigger ? ?0.4 ? 0.35v dd v v hys cc d input hysteresis cmos schmitt trigger ?0.1v dd ?? v v ol cc p output low level push pull, i ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ? ? 0.1v dd v d push pull, i ol = 1 ma, v dd = 5.0 v 10%, pad3v5v = 1 2 2 this is a transient configuration during power-up, up to the end of reset phase2 (refer to reset generation module (rgm) section of the device reference manual). ? ? 0.1v dd c push pull, i ol = 1 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ?? 0.5 t tr cc t output transition time output pin 3 medium configuration 3 c l includes device and package capacitance (c pkg <5 pf). c l = 25 pf, v dd = 5.0 v 10%, pad3v5v = 0 ? ? 10 ns tc l = 50 pf, v dd = 5.0 v 10%, pad3v5v = 0 ?? 20 tc l = 100 pf, v dd = 5.0 v 10%, pad3v5v = 0 ?? 40 tc l = 25 pf, v dd = 3.3 v 10%, pad3v5v = 1 ?? 12 tc l = 50 pf, v dd = 3.3 v 10%, pad3v5v = 1 ?? 25 tc l = 100 pf, v dd = 3.3 v 10%, pad3v5v = 1 ?? 40 w frst sr p reset input filtered pulse ? ? ? 40 ns w nfrst sr p reset input not filtered pulse ? 1000 ? ? ns i wpu cc p weak pull-up current absolute value ?10?150a d run current during reset before flash is ready ? 10 ? ma after flash is ready ? 20 ? ma
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 86 3.11 fast external crystal o scillator (4?16 mhz) electrical characteristics the device provides an oscillator/resonator driver. figure 17 describes a simple model of the internal oscillat or driver and provides an example of a connection for an oscillator or a resonator. figure 17. crystal oscillator and resonator connection scheme note xtal/extal must not be directly used to drive external circuits. table 40. crystal description nominal frequency (mhz) ndk crystal reference crystal equivalent series resistance esr ? crystal motional capacitance (c m ) ff crystal motional inductance (l m ) mh load on xtalin/xtalout c1 = c2 (pf) 1 shunt capacitance between xtalout and xtalin c0 2 (pf) 4 nx8045gb 300 2.68 591.0 21 2.93 8 nx5032ga 300 2.46 160.7 17 3.01 10 150 2.93 86.6 15 2.91 12 120 3.11 56.5 15 2.93 16 120 3.90 25.3 10 3.00 c l c l crystal extal xtal resonator extal xtal device device device extal xtal i r v dd
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 87 figure 18. fast external crystal oscillator (4?16 mhz) electrical characteristics 1 the values specified for c1 and c2 are the same as used in simulations. it should be ensured that the testing includes all the parasitics (from the board, probe, crystal, et c.) as the ac / transient behavior depends upon them. 2 the value of c0 specified here includes 2 pf additional capacitance for parasitics (to be seen with bond-pads, package, etc.). table 41. resonator description cstcr4m00g53-r0 cstcr4m00g55-r0 vibration fundamental fr (khz) 3929.50 3898.00 fa (khz) 4163.25 4123.00 fa?fr (df) (khz) 233.75 225.00 ra (k ? ) 372.41 465.03 r1 ( ? ) 12.78 11.38 l1 (mh) 0.84443 0.88244 c1 (pf) 1.94268 1.88917 co (pf) 15.85730 15.90537 qm 1630.93 1899.77 cl1 (nominal) (pf) 15 39 cl2 (nominal) (pf) 15 39 v fxoscop t fxoscsu v xtal v fxosc valid internal clock 90% 10% 1/f fxosc s_mtrans bit (me_gs register) ?1? ?0?
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 88 3.12 slow external crystal oscillator (32 khz) electrical characteristics the device provides a low power oscillator/resonator driver. table 42. fast external crystal oscillator (4?16 mhz) electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ?40 to 105 c, unless otherwise specified value unit min typ max f fxosc sr ? fast external crystal oscillator frequency ? 4.0 ? 16.0 mhz g mfxosc cc c fast external crystal oscillator transconductance v dd = 3.3 v 10%, pad3v5v = 1 oscillator_margin = 0 2.2 ? 8.2 ma/v cc p v dd = 5.0 v 10%, pad3v5v = 0 oscillator_margin = 0 2.0 ? 7.4 cc c v dd = 3.3 v 10%, pad3v5v = 1 oscillator_margin = 1 2.7 ? 9.7 cc c v dd = 5.0 v 10%, pad3v5v = 0 oscillator_margin = 1 2.5 ? 9.2 v fxosc cc t oscillation amplitude at extal f osc = 4 mhz, oscillator_margin = 0 1.3 ? ? v f osc = 16 mhz, oscillator_margin = 1 1.3 ? ? v fxoscop cc c oscillation operating point ? ? 0.95 ? v i fxosc ,2 2 stated values take into account only analog module co nsumption but not the digital contributor (clock tree and enabled peripherals) cc t fast external crystal oscillator consumption ??23ma t fxoscsu cc t fast external crystal oscillator start-up time f osc = 4 mhz, oscillator_margin = 0 ?? 6ms f osc = 16 mhz, oscillator_margin = 1 ??1.8 v ih sr p input high level cmos (schmitt trigger) oscillator bypass mode 0.65 v dd ?v dd +0.4 v v il sr p input low level cmos (schmitt trigger) oscillator bypass mode ?0.4 ? 0.35 v dd v
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 89 figure 19. crystal oscillator and resonator connection scheme note pc[14]/pc[15] must not be directly used to drive ex ternal circuits. figure 20. slow external crystal oscillator (32 khz) timing c y c x crystal pc[14] pc[15] resonator pc[14] pc[15] device device oscon bit (osc_ctl register) t sxoscsu ?1? v sxosc_xtal v sxosc valid internal clock 90% 10% 1/f sxosc ?0?
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 90 3.13 fmpll electrical characteristics the device provides a frequency-modulated phase-locked loop (fmp ll) module to generate a fast system clock from the main oscillator driver. table 43. slow external crystal oscillator (32 khz) electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ?40 to 105 c, unless otherwise specified value unit min typ max f sxosc sr t slow external crystal oscillator frequency ? 32 ? 40 khz v sxosc cc t oscillation amplitude v dd = 3.3 v 10% 1.12 1.33 1.74 v tv dd = 5.0 v 10% 1.12 1.37 1.74 i sxosc cc d slow external crystal oscillator consumption ???5a t sxoscsu cc t slow external crystal oscillator start-up time ???2 2 2 the quoted figure is based on a board that is properly laid out and has no stray capacitances. s v ih sr d input high level cmos schmitt trigger oscillator bypass mode 0.65v dd ?v dd + 0.4 v v il sr d input low level cmos schmitt trigger oscillator bypass mode ?0.4 ? 0.35v dd v table 44. fmpll electrical characteristics symbol c parameter conditions 1 1 v ddpll = 1.2 v 10%, t a = ?40 to 105 c, unless otherwise specified. value unit min typ max f pllin sr t fmpll reference clock 2 2 pllin clock retrieved directly from fxosc clock. input characteristics are granted when oscillator is used in functional mode. when bypass mode is used, oscillator input clock should verify f pllin and ? pllin . ?4?64mhz ? pllin sr t fmpll reference clock duty cycle 2 ?40?60% f pllout cc t fmpll output clock frequency ? 16 ? 64 mhz f cpu cc t system clock frequency ? ? ? 64 3 3 f cpu 64 mhz can be achieved only at temperatures up to t a = 105 c with a maximum fm depth of 2%. mhz t lock cc t fmpll lock time stable oscillator (f pllin = 16 mhz) ? ? 200 s ? t pkjit cc t fmpll jitter (peak to peak) f pllin = 16 mhz (resonator) ? ? 220 ps ? t ltjit cc t fmpll long term jitter f pllin = 16 mhz (resonator) ? ? 1.5 ns i pll cc d fmpll consumption t a = 25 c ? ? 4 ma
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 91 3.14 fast internal rc oscillator (16 mhz) electrical characteristics the device provides a 16 mhz fast internal rc oscillator. this is used as the default clock at the power-up of the device. 3.15 slow internal rc oscillator (128 khz) electrical characteristics the device provides a 128 khz slow internal rc oscillator. this can be used as the reference clock for the rtc module. table 45. fast internal rc oscillator (16 mhz) electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ?40 to 105 c, unless otherwise specified. value unit min typ max f firc cc p fast internal rc oscillator high frequency t a = 25 c, trimmed ? 16 ? mhz sr ? ? 12 20 ? fircvar cc c fast internal rc oscillator variation across temperature (t a = ?40 to 105c) and supply with respect to f firc at t a =25c in high-frequency configuration trimmed ? ?5 ? +5 % i fircrun cc d fast internal rc oscillator high frequency current in running mode t a = 25 c, trimmed ? ? ? 200 a i fircpwd cc d fast internal rc oscillator high frequency current in power down mode t a = 25 c ? ? ? 1 a i fircstop cc d fast internal rc oscillator high frequency and system clock current in stop mode t a = 25 c sysclk = off ? 0.3 ? ma d sysclk = 2 mhz ? 2 ? d sysclk = 4 mhz ? 2.5 ? d sysclk = 8 mhz ? 3.3 ? d sysclk = 16 mhz ? 5.2 ? t fircsu cc p fast internal rc oscillator start-up time v dd = 5.0 v 10% ? 1 2 s table 46. slow internal rc oscillator (128 khz) electrical characteristics symbol c parameter conditions 1 value unit min typ max f sirc cc p slow internal rc oscillator low frequency t a = 25 c, trimmed ? 128 ? khz sr ? ? 100 ? 150
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 92 3.16 flash memory electrical characteristics ? sircpre cc c slow internal rc oscillator precision after software trimming of f sirc t a = 25 c ? 2? +2% ? sirctrim cc c slow internal rc oscillator trimming step ??2.7? ? sircvar cc c slow internal rc oscillator variation across temperature (t a = ?40c to 105c) and supply with respect to f sirc at t a = 25 c in high frequency configuration trimmed ?10% ? +10% khz i sirc cc d slow internal rc oscillator low frequency current t a = 25 c, trimmed ? ? 5 a t sircsu cc c slow internal rc oscillator start-up time t a = 25 c, v dd = 5.0 v 10% ? 8 12 s 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ?40 to 105 c, unless otherwise specified. table 47. program and erase specifications symbol c parameter value unit typ 1 1 typical program and erase times assume nominal supply values and operation at 25 c. initial max 2 2 initial factory condition: < 100 program/erase cycles, 25 c, typical supply voltage. max 3 3 the maximum program and erase times occur after the spec ified number of program/erase cycles. these maximum values are characterized but not guaranteed. t dwprogram cc c double word (64 bits) program time 4 4 actual hardware programming times. this does not include software overhead. 22 50 500 s t 16kpperase cc c 16 kb block pre-program and erase time 300 500 5000 ms t 32kpperase cc c 32 kb block pre-program and erase time 400 600 5000 ms t 128kpperase cc c 128 kb block pre-program and erase time 800 1300 7500 ms t eslat cc d erase suspend latency ? 30 30 s table 46. slow internal rc oscillator (128 khz) electrical characteristics (continued) symbol c parameter conditions 1 value unit min typ max
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 93 3.17 adc electrical characteristics the device provides a 10-bit successive approximatio n register (sar) analog to digital converter. table 48. flash module life symbol c parameter conditions value unit min typ p/e cc c number of program/erase cycles per block for 16 kb blocks over the operating temperature range (t j ) ? 100000 ? cycles p/e cc c number of program/erase cycles per block for 32 kb blocks over the operating temperature range (t j ) ? 10000 100000 cycles p/e cc c number of program/erase cycles per block for 128 kb blocks over the operating temperature range (t j ) ? 1000 100000 cycles retention cc c minimum data retention at 85 c average ambient temperature 1 1 ambient temperature averaged over duration of applic ation, not to exceed recommended product operating temperature range. blocks with 0?1,000 p/e cycles 20 ? years blocks with 10,000 p/e cycles 10 ? years blocks with 100,000 p/e cycles 5 ? years table 49. flash memory read access timing symbol c parameter condition 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ?40 to 105 ? c, unless otherwise specified max value unit f read cc p maximum frequency for flash memory reading 2 wait states 64 mhz c 1 wait state 40 c 0 wait states 20
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 94 figure 21. adc characteristics and error definitions 3.17.1 input impedance and adc accuracy in the following analysis, the input circuit corres ponding to the precise ch annels is considered. to preserve the accuracy of the a/d converter, it is necessary that analog input pins have low ac impedance. placing a capacito r with good high frequency characteristics at the input pin of th e device can be effective: the capacitor should be as large as possible, ideally infinite. this capacitor contributes to attenuat ing the noise present on the input pin; furthermore, it sourc es charge during the sampling phase, when the anal og signal source is a high-impedance source. a real filter can typically be obtained by using a series re sistance with a capacitor on the input pin (simple rc filter). the rc filtering may be limited according to the value of source impedance of the tr ansducer or circuit supp lying the analog signal to be measured. the filter at the input pins mu st be designed taking into account the d ynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the adc itself. (2) (1) (3) (4) (5) offset error ose offset error ose gain error ge 1 lsb (ideal) v in(a) (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) differential non-linearity error (dnl) (4) integral non-linearity error (inl) (5) center of a step of the actual transfer curve code out 1023 1022 1021 1020 1019 1018 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 1 lsb ideal = v dda / 1024
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 95 in fact a current sink contri butor is represented by the charge shari ng effects with the sampling capacitance: c s being substantially a switched capacitance, with a frequency equal to the conversion rate of the adc, it can be seen as a resistive p ath to ground. for instance, assuming a conversion rate of 1 mhz, with c s equal to 3 pf, a resistance of 330 k ? is obtained (r eq = 1 / (f c ? c s ), where f c represents the conversion rate at the considered channel). to mini mize the error induced by the voltage partitioning between this resistance (sampled voltage on c s ) and the sum of r s + r f + r l + r sw + r ad , the external circuit must be designed to respect the equation 7 : eqn. 7 equation 7 generates a constraint for external network design, in pa rticular on resistive path. in ternal switch resistances (r sw and r ad ) can be neglected with respect to external resistances. figure 22. input equivalent circuit (precise channels) v a r s r f r l r sw r ad +++ + r eq --------------------------------------------------------------------------- ? 1 2 -- -lsb ? r s source impedance r f filter resistance c f filter capacitance r l current limiter resistance r sw1 channel selection switch impedance r ad sampling switch impedance c p pin capacitance (two contributions, c p1 and c p2 ) c s sampling capacitance c p1 r ad channel selection v a
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 96 figure 23. input equivalent circuit (extended channels) a second aspect involving the capacitance network sha ll be considered. assuming the three capacitances c f , c p1 and c p2 are initially charged at the source voltage v a (refer to the equivalent circuit reported in figure 22 ): a charge sharing phenomenon is installed when the sampling phase is started (a/d switch close). figure 24. transient behavior during sampling phase in particular two different transient periods can be distinguished: ? a first and quick charge transfer from the internal capacitance c p1 and c p2 to the sampling capacitance c s occurs (c s is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which c p2 is reported in parallel to c p1 (call c p = c p1 + c p2 ), the two capacitances c p and c s are in series, and the time constant is r f c f r s r l r sw1 c p3 c s v dd sampling source filter current limiter external circuit internal circuit scheme r s source impedance r f filter resistance c f filter capacitance r l current limiter resistance r sw channel selection switch impedance (two contributions r sw1 and r sw2 ) r ad sampling switch impedance c p pin capacitance (three contributions, c p1 , c p2 and c p3 ) c s sampling capacitance c p1 r ad channel selection v a c p2 extended r sw2 switch v a v a1 v a2 t t s v cs voltage transient on c s ? v < ? 0.5 lsb ? 1 2 ? 1 < (r sw + r ad ) c s << t s ? 2 = r l (c s + c p1 + c p2 )
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 97 eqn. 8 equation 8 can again be simplifi ed considering only c s as an additional worst condition. in reality, the transient is faster, but the a/d converter circuitry has been designed to be robust also in the very worst case: the sampling time t s is always much longer than the internal time constant: eqn. 9 the charge of c p1 and c p2 is redistributed also on c s , determining a new value of the voltage v a1 on the capacitance according to equation 10 : eqn. 10 ? a second charge transfer involves also c f (that is typically bigger than the on- chip capacitance) through the resistance r l : again considering the worst case in which c p2 and c s were in parallel to c p1 (since the time constant in reality would be faster), the time constant is: eqn. 11 in this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time t s , a constraints on r l sizing is obtained: eqn. 12 of course, r l shall be sized also according to the current limitation constr aints, in combination with r s (source impedance) and r f (filter resistance). being c f definitively bigger than c p1 , c p2 and c s , then the final voltage v a2 (at the end of the charge transfer tr ansient) will be mu ch higher than v a1 . equation 13 must be respected (charge balance assuming now c s already charged at v a1 ): eqn. 13 the two transients above are not influenced by th e voltage source that, due to the presence of the r f c f filter, is not able to provide the extra charge to comp ensate the voltage drop on c s with respect to the ideal source v a ; the time constant r f c f of the filter is very high with respect to the sampling time (t s ). the filter is ty pically designed to act as anti-aliasing. ? 1 r sw r ad + ?? = c p c s ? c p c s + --------------------- ? ? 1 r sw r ad + ?? ? c s t s ? ? ?? ? v a c p1 c p2 + ?? ? = ? 2 r l ? c s c p1 c p2 ++ ?? ? ? 2 ? 10 r l c s c p1 c p2 ++ ?? ? ? =t s ? ?? ? v a c f ? v a1 +c p1 c p2 +c s + ?? ? =
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 98 figure 25. spectral representation of input signal calling f 0 the bandwidth of the source signal (and as a conseque nce the cut-off frequency of the anti-aliasing filter, f f ), according to the nyquist theorem the conversion rate f c must be at least 2f 0 ; it means that the constant ti me of the filter is greater than or at least equal to twice the conversion period (t c ). again the conversion period t c is longer than the sampling time t s , which is just a portion of it, even when fixed channel continu ous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter r f c f is definitively much higher than the sampling time t s , so the charge level on c s cannot be modified by the analog signal source during the time in which the sampling switch is closed. the considerations above lead to impose new constraints on the external circuit, to reduce the accur acy error due to the voltag e drop on c s ; from the two charge balance equations above, it is simple to derive equation 14 between the ideal and real sampled voltage on c s : eqn. 14 from this formula, in the worst case (when v a is maximum, that is for instance 5 v ), assuming to accept a maximum error of half a count, a constraint is evident on c f value: eqn. 15 3.17.2 adc conversion characteristics note for input leakage curr ent specification, see table 30 . f 0 f analog source bandwidth (v a ) f 0 f sampled signal spectrum (f c = conversion rate) f c f anti-aliasing filter (f f = rc filter pole) f f 2 f 0 ?? f c (nyquist) f f ? f 0 (anti-aliasing filtering condition) t c ?? 2 r f c f (conversion rate vs. filter pole) noise v a v a2 ----------- - c p1 c p2 +c f + c p1 c p2 +c f c s ++ ------------------------------------------------------- - = c f 2048 c s ? ?
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 99 table 50. adc conversion characteristics symbol c parameter conditions 1 value unit min typ max v ssa sr d voltage on vssa (adc reference) pin with respect to ground (v ss ) 2 ? ?0.1 ? 0.1 v v dda sr d voltage on vdda pin (adc reference) with respect to ground (v ss ) ?v dd ?0.1 ? v dd + 0.1 v v ainx sr d analog input voltage 3 ?v ssa ?0.1 ? v dda + 0.1 v f adc sr d adc analog frequency 4 ? 6 ? 32 mhz t adc_pu sr d adc power up delay ? ? ? 1.5 s t adc_s cc t sample time 5,6 f adc = 32 mhz, adc_conf_sample_input = 17 0.5 ? ? s t f adc = 6 mhz, adc_conf_sample_input = 127 ??21 t adc_c cc t conversion time 7 f adc = 32 mhz, adc_conf_comp = 2 0.625 ? ? s c s cc d adc input sampling capacitance ?? ? 3 pf c p1 cc d adc input pin capacitance 1 ? ?? 3 pf c p2 cc d adc input pin capacitance 2 ??? 1 pf c p3 cc d adc input pin capacitance 3 ??? 1 pf r sw1 cc d internal resistance of analog source ? ? ? 1 k ? r sw2 cc d internal resistance of analog source ??? 1 k ? r ad cc d internal resistance of analog source ??? 0.1 k ? i inj sr t input current injection current injection on one adc input, different from the converted one ?5 ? 5 ma inl cc p integral non linearity no overload ? .5 ? 2.5 lsb dnl cc p differential non linearity no overload ?1.0 ? 1.0 lsb ofs cc t offset error after offset cancellation ? 0.5 ? lsb gne cc t gain error ? ? 0.6 ? lsb tuex cc p total unadjusted error for extended channel without current injection ?3 ? 3 lsb t with current injection ?4 ? 4
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 100 3.18 lcd driver electrical characteristics 3.19 pad ac specifications 1 v dda = 3.3 v 10% / 5.0 v 10%, t a = ?40 to 105 c, unless otherwise specified. 2 analog and digital v ss must be common (to be tied together externally). 3 v ainx may exceed v ssa and v dda limits, remaining on absolute maximum ra tings, but the results of the conversion will be clamped respectively to 0x000 or 0x3ff. 4 at 32 mhz the minimum sampling time must be at least 180 ns. 5 during the sample time the input capacitance c s can be charged/discharged by the external source. the internal resistance of the analog source must allow the c apacitance to reach its final voltage level within t adc_s . after the end of the sample time t adc_s , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t adc_s depend on programming. 6 the maximum sample rate is 1 million samples per second, provided the source impedance and current limiter(> 1 k ? ) are calculated adequately. ? filter capacitor at analog source output must meet the criteria cf (filter capacitor) > 2048 cs (sampling capacitor is 3 pf). 7 this parameter does not include the sample time t adc_s , but only the time for determining the digital result and the time to load the result?s register with the conversion result. table 51. lcd driver specifications symbol c parameter value 1 1 v dd =5.0v10%, t a = ?40?105 c, unless otherwise specified unit min typ max vlcd sr c voltage on vlcd (lcd supply) pin with respect to vss 0 ? vdde + 0.3 v z bp/fp cc t lcd output impedance (bp[n-1:0],fp[m-1:0]) for output levels vlcd, vss 2 2 outputs measured one at a time, low impedance voltage source connected to the vlcd pin. ??5.0k ? i bp/fp cc t lcd output current (bp[n-1:0],fp[m-1:0]) for outputs charge/discharge voltage levels vlcd2/3, vlcd1/2, vlcd1/3) 2 , 3 3 with pwr=10, bsten=0, and bstao=0 ?25? ? a table 52. pad ac specifications (5.0 v, pad3v5v = 0) 1 no. pad tswitchon 1 (ns) rise/fall 2 (ns) frequency (mhz) current slew (ma/ns) load drive (pf) min typ max min typ max min typ max min typ max 1 slow 1.5 ? 30 6 ? 50 ? ? 4 0.04 ? 2 25 1.5 ? 30 9 ? 100 ? ? 2 0.04 ? 2 50 1.5 ? 30 12 ? 125 ? ? 2 0.04 ? 2 100 1.5 ? 30 16 ? 150 ? ? 2 0.04 ? 2 200
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 101 2 medium 1 ? 15 3 ? 10 ? ? 40 2.5 ? 7 25 1 ? 15 5 ? 20 ? ? 20 2.5 ? 7 50 1 ? 15 9 ? 40 ? ? 13 2.5 ? 8 100 1 ? 15 12 ? 70 ? ? 7 2.5 ? 8 200 3 fast 1 ? 6 1 ? 4 ? ? 100 18 ? 55 25 1 ? 6 1.5 ? 6 ? ? 80 18 ? 55 50 1 ? 6 3 ?12??4018?55 100 1 ? 6 5 ?16??2518?55 200 4 pull up/down (5.5 v max) ?????5000?????? 50 parameter classification dcccn/a 1 propagation delay from v dd /2 of internal signal to pchannel/nchannel on condition 2 slope at rising/falling edge table 53. pad ac specifications (3.3 v, pad3v5v = 1) 1 no. pad tswitchon 1 (ns) rise/fall 2 (ns) frequency (mhz) current slew (ma/ns) load drive (pf) min typ max min typ max min typ max min typ max 1 slow 3 ? 40 4 ? 40 ? ? 4 0.01 ? 2 25 3?406?50??20.01?2 50 3 ? 40 10 ? 75 ? ? 2 0.01 ? 2 100 3 ? 40 14 ? 100 ? ? 2 0.01 ? 2 200 2 medium 1 ? 15 2 ? 12 ? ? 40 2.5 ? 7 25 1 ? 15 4 ? 25 ? ? 20 2.5 ? 7 50 1 ? 15 8 ? 40 ? ? 13 2.5 ? 7 100 1 ? 15 14 ? 70 ? ? 7 2.5 ? 7 200 table 52. pad ac specifications (5.0 v, pad3v5v = 0) 1 (continued) no. pad tswitchon 1 (ns) rise/fall 2 (ns) frequency (mhz) current slew (ma/ns) load drive (pf) min typ max min typ max min typ max min typ max
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 102 figure 26. pad output delay 3 fast 1 ? 6 1 ? 4 ??72 3 ?40 25 1?61.5?7??553?40 50 1 ? 6 3 ?12??40 3 ?40 100 1 ? 6 5 ?18??25 3 ?40 200 4 pull up/down (3.6 v max) ?????7500?????? 50 parameter classification dcccn/a 1 propagation delay from v dd /2 of internal signal to pchannel/nchannel on condition 2 slope at rising/falling edge table 53. pad ac specifications (3.3 v, pad3v5v = 1) 1 (continued) no. pad tswitchon 1 (ns) rise/fall 2 (ns) frequency (mhz) current slew (ma/ns) load drive (pf) min typ max min typ max min typ max min typ max v dd /2 v oh v ol rising edge output delay falling edge output delay pad data input pad output
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 103 3.20 ac timing 3.20.1 ieee 1149.1 interface timing table 54. smd pad delays symbol c parameter conditions value unit min typ max ? cc d smd pad delay cl=50pf v dd =5v10% sre=1 ??165ns cl=50pf v dd =5v10% sre=0 ??35ns ? cc d smd pad delay cl=50pf v dd =3.3v10% sre=1 ??350ns cl=50pf v dd =3.3v10% sre=0 ??50ns table 55. jtag interface timing 1 1 these specifications apply to jtag boundar y scan only. jtag timing specified at v dd = 3.0 v to 5.5 v, t a = ?40 to 105 c, and c l = 50 pf with src = 0b11. no. symbol c parameter value unit min max 1t jcyc cc d tck cycle time 100 ? ns 2t jdc cc d tck clock pulse width (measured at v dd /2) 40 60 ns 3t tckrise cc d tck rise and fall times (40%?70%) ? 3 ns 4t tmss, t tdis cc d tms, tdi data setup time 5 ? ns 5t tmsh, t tdih cc d tms, tdi data hold time 10 ? ns 6t tdov cc d tck low to tdo data valid ? 40 ns 7t tdoi cc d tck low to tdo data invalid 0 ? ns 8t tdohz cc d tck low to tdo high impedance ? 30 ns
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 104 figure 27. jtag test clock input timing figure 28. jtag test access port timing tck 1 2 2 3 3 tck 4 5 6 7 8 tms, tdi tdo
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 105 figure 29. jtag boundary scan timing 3.20.2 nexus debug interface table 56. nexus debug port timing 1 no. symbol c parameter value unit min max 1t mcyc cc d mcko cycle time 22 ? ns 2 ? mdc cc d mcko duty cycle 40 60 % 3t mdov cc d mcko low to mdo data valid 2 ?2 14 ns 4t mseov cc d mcko low to mseo data valid 2 ?2 14 ns 5t evtov cc d mcko low to evto data valid 2 ?2 14 ns 6t evtipw cc d evti pulse width 4 ? t tcyc 7t evtopw cc d evto pulse width 1 ? t mcyc tck output signals input signals output signals 9 10 11 12 13
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 106 figure 30. nexus output timing figure 31. nexus tck timing 8t tcyc cc d tck cycle time 3 100 ? ns 9 ? tdc cc d tck duty cycle 40 60 % 10 t ntdis, t ntmss cc d tdi, tms data setup time 10 ? ns 11 t ntdih, t ntmsh cc d tdi, tms data hold time 5 ? ns 12 t jov cc d tck low to tdo data valid 0 40 ns 1 jtag specifications in this table apply when used for deb ug functionality. all nexus timing relative to mcko is measured from 50% of mcko and 50% of the respective signal. nexus timing specified at v dd = 3.0 v to 5.5v, t a = ?40 to 105 c, and c l = 50 pf (c l = 30 pf on mcko), with src = 0b11. 2 mdo, mseo , and evto data is held valid until next mcko low cycle. 3 the system clock frequency needs to be three times faster than the tck frequency. table 56. nexus debug port timing 1 (continued) no. symbol c parameter value unit min max 1 2 4 5 mcko mdo mseo evto output data valid 3 tck 8 9 9
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 107 figure 32. nexus tdi, tms, tdo timing 3.20.3 interface to tft lcd panels figure 33 depicts the lcd interface timing for a ge neric active matrix color tft panel. in this figure signals are shown with positive polarity. th e sequence of events for activ e matrix interface timing is: 1. dcu_clk latches data into the panel on its positive edge (when positive polarity is selected). in active mode, dcu_clk runs continuously. 2. dcu_hsync causes the panel to start a new line. it always encompasses at least one pclk pulse. 3. dcu_vsync causes the panel to start a new frame. it always encompasses at least one hsync pulse. 4. dcu_de acts like an output enable signal to the lcd panel. this output enables the data to be shifted onto the display. when disabled, the data is invalid and the trace is off. tdo 10 11 tms, tdi 12 tck
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 108 figure 33. tft lcd interface timing overview 1 3.20.3.1 interface to tft lcd panels?pixel level timings figure 34 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and data. all parameters shown in the diagram are programmable. this timing diagra m corresponds to positive polarity of the dcu_clk signal (meaning the data and sync signals cha nge on the rising edge) and active-high polarity of the dcu_hsync, dcu_vsync and dcu_de signals. the user can select the polarity of the dcu_hsync and dcu_vsync signals via the syn_pol register, whether active-high or active- low. the default is active-high. the dcu_de signal is always active-high. pixel clock inversion and a flexible programmable pixel cloc k delay are also supported. they are programmed via the dcu clock confide register (dccr) in the system clock module. the delta_x and delta_y parameters are programmed vi a the disp_size register. the pw_h, bp_h and fp_h parameters are programmed via the hsyn para register. the pw_v, bp_v and fp_v parameters are programmed via the vsyn_para register. 1. in figure 33 , the ?dcu_ld[23:0]? signal is an aggregation of the dcu?s rgb signals?dc u_r[0:7], dcu_ g[0:7] and dcu_b[0:7]. table 57. lcd interface timing parameters?horizontal and vertical symbol c parameter value unit t pcp cc d display pixel clock period ? ns t pwh cc d hsync pulse width pw_h ? t pcp ns t bph cc d hsync back porch width bp_h ? t pcp ns t fph cc d hsync front porch width fp_h ? t pcp ns t sw cc d screen width delta_x ? t pcp ns t hsp cc d hsync (line) period (pw_h + bp_h + fp_h + delta_x ) ? t pcp ns t pwv cc d vsync pulse width pwv ??? t hsp ns line 1 line 2 line 3 line 4 line n-1 line n dcu_vsync dcu_hsync dcu_hsync dcu_de dcu_clk dcu_ld[23:0] 2 13 m-1m
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 109 figure 34. horizontal sync timing figure 35. vertical sync pulse t bpv cc d vsync back porch width bp_v ? t hsp ns t fpv cc d vsync front porch width fp_v ? t hsp ns t sh cc d screen height delta_y ? t hsp ns t vsp cc d vsync (frame) period (pw_v + bp_v + fp_v + delta_y ) ? t hsp ns table 57. lcd interface timing parameters?horizontal and vertical (continued) symbol c parameter value unit start of line dcu_clk dcu_ld[23:0] dcu_hsync dcu_de t pwh t bph t hsp t sw t pcp t fph 12 3 delta_x invalid data invalid data start of frame dcu_hsync dcu_ld[23:0] dcu_hsync dcu_de t pwv t bpv t vsp t hcp t fpv 1 2 3 delta_y invalid data invalid data (line data) t sh
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 110 3.20.3.2 interface to tft lcd panels figure 36. tft lcd interface timing parameters table 58. tft lcd interface timing parameters 1,2,3,4 1 the characteristics in this table are based on the assumption that data is output at positive edge and displays latch data on negative edge. 2 intra bit skew is less than 2 ns. 3 load c l = 50 pf for panel frequency up to 20 mhz. 4 load c l = 25 pf for panel frequency from 20 to 32 mhz. symbol c parameter value unit min typ max t ckp cc d pdi clock period 15.25 ? ? ns ? ck cc d pdi clock duty cycle 40 ? 60 % t dsu cc d pdi data setup time 9.5 ? ? ns t dhd cc d pdi data access hold time 4.5 ? ? ns t csu cc d pdi control signal setup time 9.5 ? ? ns t chd cc d pdi control signal hold time 4.5 ? ? ns cc d tft interface data valid after pixel clock ? ? 6 ns cc d tft interface vsync valid after pixel clock ? ? 5.5 ns cc d tft interface de valid after pixel clock ? ? 5.6 ns cc d tft interface hold time for data and control bits 2 ? ? ns cc d relative skew between the data bits ? ? ?3.7ns dcu_hsync dcu_vsync dcu_de dcu_clk dcu_ld[23:0] t ckh t ckl t chd t csu t dhd t dsu
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 111 3.20.4 external interrupt (irq) and no n-maskable interrupt (nmi) timing figure 37. irq and nmi timing 3.20.5 emios timing table 59. irq and nmi timing no. symbol c parameter value unit min max 1t ipwl cc t irq/nmi pulse width low 200 ? ns 2t ipwh cc t irq/nmi pulse width high 200 ? ns 3t icyc cc t irq/nmi edge to edge time 1 1 applies when irq/nmi pins are configured for rising edge or falling edge events, but not both. 400 ? ns table 60. emios timing 1 1 emios timing specified at f sys = 64 mhz, v dd12 = 1.14 v to 1.32 v, vdde_x = 3.0 v to 5.5 v, t a = ?40 to 105 c, and c l = 50 pf with src = 0b00. no. symbol c parameter value unit min 2 2 there is no limitation on the peripheral for setting the minimum pulse width, the ac tual width is restricted by the pad delays. refer to the pad specification section for the details. max 1t mipw cc d emios input pulse width 4 ? t cyc 2t mopw cc d emios output pulse width 1 ? t cyc 1,2 3 1,2
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 112 3.20.6 flexcan timing the can functions are available as tx pins at normal i/o pads and as rx pins at the always on domain. there is no filter for the wakeup dominant pulse. any high-to-low edge can cause wakeup if configured. 3.20.7 deserial serial peripheral interface (dspi) table 61. flexcan timing 1 1 flexcan timing specified at f sys = 64 mhz, v dd12 = 1.14 v to 1.32 v, vdde_x = 3.0 v to 5.5 v, t a = ?40 to 105 c, and c l = 50 pf with src = 0b00. no. symbol c parameter value unit min max 1t canov cc d ctnx output valid after clkout rising edge (output delay) ? 22.48 ns 2t cansu cc d cnrx input valid to clkout rising edge (setup time) ? 12.46 ns table 62. dspi timing 1 no. symbol c parameter conditions value unit min max 1t sck cc d dspi cycle time 2,3 master (mtfe = 0) slave (mtfe = 0) slave receive only mode 62 62 62 ? ? ? ns ns ns 2t csc cc d pcs to sck delay 4 ?20?ns 3t asc cc d after sck delay 5 ?20?ns 4t sdc cc d sck duty cycle ? 0.4 x t sck 0.6 x t sck ns 5t a cc d slave access time (pcsx active to sout driven) ss active to sout valid ? 40 ns 6t dis cc d slave sout disable time (pcsx inactive to sout high-z or invalid) ss inactive to sout high-z or invalid ? 10 ns 7t pcsc pcsx to pcss time ? 20 ?ns 8t pasc pcss to pcsx time ? 20 ?ns 9t sui cc d data setup time for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) 6 master (mtfe = 1, cpha = 1) 35 2 20 35 ? ? ? ? ns ns ns ns 10 t hi cc d data hold time for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) 6 master (mtfe = 1, cpha = 1) ?5 5 10 ?5 ? ? ? ? ns ns ns ns
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 113 figure 38. dspi classic spi timing ? master, cpha = 0 11 t suo cc d data valid (after sck edge) master (mtfe = 0) slave master (mtfe = 1, cpha = 0) master (mtfe = 1, cpha = 1) ? ? ? ? 14 39 24 15 ns ns ns ns 12 t ho cc d data hold time for outputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) master (mtfe = 1, cpha = 1) ?3 6 12 ?3 ? ? ? ? ns ns ns ns 1 dspi timing specified at vdde_x = 3.0 v to 5.5 v, t a = ?40 to 105 c, and c l = 50 pf with src = 0b11. 2 the minimum sck cycle time restricts the baud rate selection for given system clock rate. 3 the actual minimum sck cycle time is limited by pad performance. 4 the maximum value is programmable in dspi_cta rx[pssck] and dspi_ctarx[cssck], program pssck = 2 and cssck = 2. 5 the maximum value is programmable in dspi_ctarx[pasc] and dspi_ctarx[asc]. 6 this delay value is corresponding to smpl_pt = 00b, which is bit field 9 and 8 of dspi_mcr register. table 62. dspi timing 1 (continued) no. symbol c parameter conditions value unit min max data last data first data first data data last data sin sout pcsx sck output 4 7 10 1 9 8 4 sck output (cpol = 0) (cpol = 1) 3 2 note: numbers in circles refer to values in ta b l e 6 2 .
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 114 figure 39. dspi classic spi timing ? master, cpha = 1 figure 40. dspi classic spi timing ? slave, cpha = 0 data last data first data sin sout 10 9 8 last data data first data sck output sck output pcsx 7 (cpol = 0) (cpol = 1) note: numbers in circles refer to values in ta b l e 6 2 . last data first data 3 4 1 data data sin sout pcsx 4 5 6 7 9 8 10 sck input first data last data sck input 2 (cpol = 0) (cpol = 1) note: numbers in circles refer to values in ta b l e 6 2 .
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 115 figure 41. dspi classic spi timing ? slave, cpha = 1 figure 42. dspi modified transfer format timing ? master, cpha = 0 5 6 7 10 9 8 last data last data sin sout pcsx first data first data data data sck input sck input (cpol = 0) (cpol = 1) note: numbers in circles refer to values in ta b l e 6 2 . pcsx 3 1 4 8 4 7 10 9 sck output sck output sin sout first data data last data first data data last data 2 (cpol = 0) (cpol = 1) note: numbers in circles refer to values in ta b l e 6 2 .
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 116 figure 43. dspi modified transfer format timing ? master, cpha = 1 figure 44. dspi modified transfer format timing ? slave, cpha = 0 pcsx 8 7 10 9 sck output sck output sin sout first data data last data first data data last data (cpol = 0) (cpol = 1) note: numbers in circles refer to values in ta b l e 6 2 . last data first data 3 4 1 data data sin sout pcsx 4 5 6 7 9 8 sck input first data last data sck input 2 (cpol = 0) (cpol = 1) 10 note: numbers in circles refer to values in ta b l e 6 2 .
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 117 figure 45. dspi modified transfer format timing ? slave, cpha = 1 3.20.8 i 2 c timing table 63. i 2 c input timing specifications ? scl and sda no. symbol c parameter value unit min max 1 ? cc d start condition hold time 2 ? ip-bus cycle 1 1 inter peripheral clock is the clock at which the i 2 c peripheral is working in the device. 2 ? cc d clock low time 8 ? ip-bus cycle 1 4 ? cc d data hold time 0.0 ? ns 6 ? cc d clock high time 4 ? ip-bus cycle 1 7 ? cc d data setup time 0.0 ? ns 8 ? cc d start condition setup time (for repeated start condition only) 2 ? ip-bus cycle 1 9 ? cc d stop condition setup time 2 ? ip-bus cycle 1 5 6 7 10 9 8 last data last data sin sout pcsx first data first data data data sck input sck input (cpol = 0) (cpol = 1) note: numbers in circles refer to values in ta b l e 6 2 .
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 118 figure 46. i 2 c input/output timing 3.20.9 quadspi timing the following notes apply to table 65 : ? all data are based on a negative edge data launch from mp c5606s and a positive edge data capture as shown in the timing diagrams. ? typical values are provided from center-split material at 25 ? c and 3.3 v. minimum and maximum values are from a temperature variation of ?45 ? c to 105 ? c and the following supply conditions: ? i/o voltage: 3.2 v, core supply: 1.2 v ? i/o voltage: 3.6 v, core supply: 1.2 v ? all measurements are taken at 70% of vdde levels for clock pin and 50% of vdde level for data pins. table 64. i 2 c output timing specifications ? scl and sda no. symbol c parameter value unit min max 1 1 1 programming ibfd (i 2 c bus frequency divider) with the maximum frequency results in the minimum output timings listed. the i 2 c interface is designed to scale the data transition ti me, moving it to the middle of the scl low period. the actual position is affected by the presca le and division values programmed in ifdr. ? cc d start condition hold time 6 ? ip-bus cycle 2 2 inter peripheral clock is the clock at which the i 2 c peripheral is working in the device. 2 1 ? cc d clock low time 10 ? ip-bus cycle 1 3 3 3 because scl and sda are open-drain-type outputs, which the processor can only actively drive low, the time scl or sda takes to reach a high level depends on external signal capacitance and pull-up resistor values. ? cc d scl/sda rise time ? 99.6 ns 4 1 ? cc d data hold time 7 ? ip-bus cycle 1 5 1 ? cc d scl/sda fall time ? 99.5 ns 6 1 ? cc d clock high time 10 ? ip-bus cycle 1 7 1 ? cc d data setup time 2 ? ip-bus cycle 1 8 1 ? cc d start condition setup time (for repeated start condition only) 20 ? ip-bus cycle 1 9 1 ? cc d stop condition setup time 10 ? ip-bus cycle 1 scl sda 1 2 3 4 5 6 7 89
electrical characteristics mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 119 ? timings correspond to qspi_smpr = 0x0000_000x. see the mpc5606s microcontroller reference manual for details. ? a negative value of hold is an indication of pad delay on the clock pad (delay between the edge capturing data inside the device and the edge appearing at the pin). ? values are with a load of 15 pf on the output pins. figure 47. quadspi output timing diagram figure 48. quadspi input timing diagram table 65. quadspi timing symbol c parameter value unit min typ max t cq cc t clock to q delay 1.60 2.4 5.33 ns t s cc t setup time for incoming data 6.1 9.4 12.1 ns t h cc t hold time requirement for incoming data ?12.5 ?8.5 ?7.5 ns t r cc t clock pad rise time 0.4 0.6 1.0 ns t f cc t clock pad fall time 0.3 0.5 0.9 ns sck t cq do 1. last address out 1 t cq sck t h t s do di 1. last address out 2. address captured at flash 3. data out from flash 4. ideal data capture edge 5. delayed data capture ed ge with qspi_smpr=0x0000_000x 6. delayed data capture ed ge with qspi_smpr=0x0000_002x 7. delayed data capture ed ge with qspi_smpr=0x0000_004x 8. delayed data capture ed ge with qspi_smpr=0x0000_006x 2 3 4 5 6 7 8 1
mpc5606s microcontroller data sheet, rev. 8 electrical characteristics freescale semiconductor 120 the clock profile in figure 49 is measured at 30% to 70% levels of vdde. figure 49. quadspi clock profile t r t f 70% 30% vdde sck
package mechanical data mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 121 4 package mechanical data 4.1 144 lqfp
mpc5606s microcontroller data sheet, rev. 8 package mechanical data freescale semiconductor 122 figure 50. lqfp144 mechanical drawing (part 1 of 3)
package mechanical data mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 123 figure 51. lqfp144 mechanical drawing (part 2 of 3)
mpc5606s microcontroller data sheet, rev. 8 package mechanical data freescale semiconductor 124 figure 52. lqfp144 mechanical drawing (part 3 of 3)
package mechanical data mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 125 4.2 176 lqfp figure 53. lqfp176 mechanical drawing (part 1 of 3)
mpc5606s microcontroller data sheet, rev. 8 package mechanical data freescale semiconductor 126 figure 54. lqfp176 mechanical drawing (part 2 of 3)
package mechanical data mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 127 figure 55. lqfp176 mechanical drawing (part 3 of 3)
mpc5606s microcontroller data sheet, rev. 8 ordering information freescale semiconductor 128 5 ordering information 1 the 176-pin package is available only for chips with 1 mb flash memory. 2 208 mapbga available only as development package for nexus2+, and will not be qualified for production figure 56. commercial product code structure qualification status power architecture core automotive platform core version flash size (core dependent) product fab, mask version, mask set indicator mpc56 sf0avlu example production code: 06 temperature options package option qualification status m = general market qualified p = engineering samples s = automotive qualified automotive platform 56 = power architecture in 90nm core version 0 = e200z0 flash memory size (z0 core) 2 = 256 kb 4 = 512 kb 6 = 1 mb product version s = cluster fab, mask version, mask set indicator (only used for spc part numbers) f = atmc fab 0 = maskset version (0, 1, etc.) a = maskset indicator: blank: first production maskset a: second production maskset b: third production maskset ... shipping method r temperature spec. c = ?40 to 85 c v = ?40 to 105 c package option lq = 144 lqfp lu = 176 lqfp 1 mg = 208 mapbga 2 speed 6 = 64 mhz shipping method blank = tray r = tape and reel speed 6 example custom-build code: sc 123456 v lu r 6 custom device prefix 6-digit number fields as for production chips (see above)
revision history mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 129 6 revision history table 66. document revision history revision date substantive changes 1 10-2008 initial release. 2 18 aug 2009 editorial changes and improvements. harmonized oscillator naming throughout document features: updated description of adc channels ta b l e 2 : changed max number of gpios from 132 to 133 for lqfp176 ta b l e 3 : corrected ?peripheral interrupt timer (p it)? to ?periodic in terrupt timer (pit)? figure 2 : ? added gpios to pin function names ? changed function of pin 32: was nc?is vreg_bypass ? pin 55: changed xtal32 to osc32k_xtal ? pin 56: changed extal32 to osc32k_extal figure 5 : ? added gpios to pin function names ? changed function of pin 32: was nc?is vreg_bypass ? pin 71: changed xtal32 to osc32k_xtal ? pin 72: changed extal32 to osc32k_extal ta b l e 6 : ? removed pins extal32, xtal32 and nmi ? updated vrc_ctl i/o direction and pad type ta b l e 7 : ? replaced ?a? with ?i? in pad type column ? modified table footnote 3 to replace pad type ?a? defin ition with pad type ?i? definition ta b l e 8 : moved ma[0:2] to follow an[0:15] added section 3.2, ?paramet er classification and added classification tags to electrical characteristics tables where appropriate added section 3.3, ?nvusro register ta b l e 1 4 : removed esd hbm ta b l e 1 7 : merged 144- and 176-pin lqfp characteristics into single table added section 3.6, ?electromagnetic com patibility (emc) characteristics ta b l e 2 6 : removed ?t a = 25 c, after trimming? from conditions for v porh , v lv d h 3 v and v lv d h 5 v ta b l e 2 7 : ? changed t a = ?40 to 125 c to t a = ?40 to 105 c in note 1 ? added standby1 and standby2 mode current characteristics figure 14 : updated to reference gpdi register and values for bit pdi section 3.8.1, ?i/o pad types : corrected ?four main i/o pad types? to read ?three main i/o pad types? section 3.8.3, ?i/o output dc characteristics : replaced ipp_hve with pad3v5v
mpc5606s microcontroller data sheet, rev. 8 revision history freescale semiconductor 130 2 (continued) 18 aug 2009 (continued) ta b l e 3 7 : ? i rmsmed : replaced slow with medium in parameter column ? i rmsfst : replaced slow with fast in parameter column section 3.8.4, ?i/o pad current specification : replaced ipp_hve with pad3v5v section 3.10, ?reset elec trical characteristics : replaced ipp_hve with pad3v5v updated figure 15 updated figure 18 updated figure 20 section 3.19, ?pad ac specifications : replaced ipp_h ve with pad3v5v ta b l e 4 5 : added rows i fircstop and t fircsu ta b l e 4 6 : ? added rows t sircsu and ? sirctrim ? updated conditions for ? sircvar added ta b l e 4 2 ?adc input leakage current? ta b l e 5 0 : updated tuep and tuex ta b l e 7 : modified pc[0] to pc[9]: ? i/o direction: was i, is i/o ? pad type: was i, is s ta b l e 5 0 : updated values for ?i nput current injection? section 3.20.3, ?interface to tft lcd panels : modified description of event no. 1 in sequence for active matrix interface timing ta b l e 5 7 : removed value for display pixel clock period ta b l e 5 3 : removed duplicated row for part number mpc5604semlq section 2.4.2, ?voltage supply pins ?: added preferred power up sequence. section 2.9, ?port pin summary ?: changed reset configuration on adc pins. section 3, ?electrical characteristics : made updates to data. all data is still considered preliminary. section 3.7.1, ?voltage regulator electrical characteristics ?: added lower power voltage regulator and ultra-low power voltage regulator characteristics. 3 ? not released; no substantive changes between rev. 2 and rev. 3. 4 ? not released; no substantive changes between rev. 3 and rev. 4. table 66. document revision history revision date substantive changes
revision history mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 131 5 1 sep 2010 editorial changes and improvements. replaced ?validation? with ?characterization? throughout. added an entry for rev. 3 to this table. in the block diagram, in the sxosc block, changed ?32 khz? to ?32 khz?. revised the feature section and added the ?feature details? subsection. renamed the analog pins (were an..., are ans...) throughout. changed several pin names that contained _a, _b, _c, ... to contain _0, _1, _2, ... throughout. changed the pcs and oscillator pin names throughout. revised the feature section and added the ?feature details? subsection. deleted the out-of-date ?block summary? section. in the 144-pin pinout: ? for pin 122, changed pcs_b1 to pcs1_1. ? for pin 123, changed pcs_b0 to pcs0_1. in the ?144 lqfp package pinout? section, added pinouts for the chips with 512 kb and 256 kb flash memory. in the 176-pin pinout: ? for pin 152, changed pcs_b1 to pcs1_1. ? for pin 153, changed pcs_b0 to pcs0_1. revised the ?pad configuration during reset phases?, ?voltage supply pins?, ?pad types?, ?system pins?, and ?nexus pins? sections. changed several module names and abbrevia tions to be consistent with the official module names and abbreviations. in the ?voltage supply pin descriptions? table, revised the entry for v dd12 . in the ?debug pin descriptions? table, changed pad type m to pad type m1. in the ?pad types? section, changed ?regist ers in the device reference manual? to ?registers in the siul chapter of the device reference manual?. changed the name of the port-pin summary section (was ?functional ports a, b, c, d, e, f, g, h, i, j, k?, is ?port pin summary?). in the ?signal details? section: ? renamed the analog pins (were an..., are ans...). ? added ?ans[0:15] connect to atd chan nels [32:47]? to the ans signal description. ? added ?the available 8 multiplexed channels connect to atd channels [64:71]? to the ma signal description. ? deleted ?when high; otherwise low to allow a subframe display for pixels? from the dcu_de description. ? changed the description for dcu_tag, pdi_pclk, txd_a, and ssd signals. ? added quadspi signals. ? deleted ?for valid pixel data this is high, otherwise low? from the pdi_de description. ? changed several pin names that contained _a, _b, _c, ... to contain _0, _1, _2, ... in the ?port pin summary? table: ? changed the pad type for pc[0]?pc[9] (was s, is j). ? moved the an[0]?an[15] entries from the ?function? column to the ?special function? column. ? moved the osc32k_extal and osc32k_xta l entries from the ?function? column to the ?special function? column. ? added alternate function names and clar ifying footnotes to the pf[11]?pf[14] entries. ? added new information on pad types (incl uding splitting up the existing m pads into two categories, m1 and m2). ? added a footnote to the ?special function? column title. table 66. document revision history revision date substantive changes
mpc5606s microcontroller data sheet, rev. 8 revision history freescale semiconductor 132 5 (continued) 1 sep 2010 (continued) added a footnote to the ?pad type description? table. in the ?pad type description? table: ? revised the entry for smd. ? revised the description for the j and m2 pad types. revised the entry for vsspll in the ?absolute maximum ratings? and ?recommended operating conditions? table. changed the max value for v ddpll (was 1.32 v, is 1.4 v) in several tables. added the ?connecting power supply pins: wh at to do and what not to do? section. in the ?recommended operating conditions? ta ble, changed the note to state ?maximum slew...? instead of ?minimum slew...?. in footnote 2 of the ?recommended operat ing conditions? table, changed ?200 f capacitance must be connected between v ddr and v ss12 ? to ?10 f capacitance must be connected between v ddr and v ss12 .?. in the ?recommended operating conditions? section, added a caution on which voltages must be the same. in the ?recommended operating conditions (3.3 v)? table: ? revised the footnote affecting v dd12 /v ss12 supply capacitances. ? deleted footnote 9. ? deleted the entries for v ddpll and v dd12 . in the ?recommended operating conditions (5.0 v)? table: ? changed the footnote text ?200 f ca pacitance must be connected between v ddr and v ss12 ? to ?10 f capacitance must be connected between v ddr and v ss12 ? and revised the footnote affecting v dd12 /v ss12 supply capacitances. ? added a specification for tv dd . ? deleted the entries for v ddpll and v dd12 . revised the ?emc requirements on board? section. added meaningful values to the ?emi testing specifications? table. in the ?esd absolute maximum ratings? table, added a specification for v esd(mm) . deleted the empty ?dc electric al characteristics? section. in the ?i/o pad types? section, added an entry for smd pads. added smc pad electrical characteristics. revised the ?voltage regulator electrical characteristics? section. revised the ?low-power voltage regulator electrical characteristics? table. revised the ?ultra-low power voltage regula tor electrical characteristics? table. revised the ?low voltage monitor electrical characteristics? table. added the ?recommended power-up and power-down order? section. added the ?power-up inrush current profile? section. added the ?hpreg load regulation characteristics? section. revised the ?dc electrical characteristics? table. replaced all values for ?standby mode current?. revised the ?i/o pad types? section. in the ?i/o input dc electrical characteristics? table: ? changed the specifications for ilkg (was min = <1 ? a, is min = ?1 ? a; was max = ?, is max = 1 ? a). ? added an entry for r on . revised the ?i/o output dc characteristics? section. revised the ?medium configur ation output buffer electrical characteristics? table. revised the ?smd pad electrical characteristics? table and changed its name (is ?smc pad...?). in the ?smc pad electrical c haracteristics? table, changed r dsoh to r dsonh and r dsol to r dsonl . moved the i max specification from the ?s mc pad electrical characteristics? table to the ?absolute maximum ratings? table. table 66. document revision history revision date substantive changes
revision history mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 133 5 (continued) 1 sep 2010 (continued) added the ?smc pad delays? table. added the ?ssd specifications? section. in the ?i/o consumption? table, added a specification for i ddmxavg . revised the ?fast external crystal oscillator ( 4?16 mhz) electrical characteristics? table. in the ?slow external crystal oscillator (3 2 khz) electrical characteristics? figure, changed v osc32k_xtal to v sxosc_xtal . in footnote 2 of the ?fmpll electrical characteristics? table, changed ?f cpu 64 mhz can be achieved only at up to 105 c? to ?f cpu 64 mhz can be achieved only at temperatures up to 105 c with a maximum fm depth of 2%?. in the first ?crystal oscillator and resonator connection scheme? figure: ? swapped ?xtal? and ?extal?. ? deleted r p . in the second ?crystal oscillator and resonator connection scheme? figure, deleted r f . added the ?crystal description? table. in the ?fast internal rc oscillator (16 mhz) electrical characteristics? table: ? changed the conditions for ? fircvar (was ?t a = ?25 c?, is ?t a = ?40 to 105 c, trimmed?), removed the associated foot note, and changed the associated guarantee method (was p, is c). ? changed the max specification for i fircpwd (was 10 ? a, is 1 ? a). added the ?resonator description? table. in the ?fast external crystal os cillator (4 to 16 mhz) electrical characteristics? table, changed footnote 1 (was ?... to 125 ? c?, is ?... to 105 ? c?). in the ?slow external crystal oscillator? section, changed ?32 khz? to ?32 khz?. in the ?slow external crystal oscillator (32 khz) electrical characteristics? table, added a footnote to the start-up timing specification. in the ?slow internal rc oscillator (128 khz) electrical characteristics? table: ? changed the condition for ? sircvar (was ?, is ?trimmed?) and the associated guarantee method (was p, is c). ? changed the guarantee method for f sirc (was p, is c). revised the ?program and erase specifications? table. in the ?flash memory read access timing? ta ble, changed footnote 1 (was ?... to 125 ? c?, is ?... to 105 ? c?). revised the ?flash module life? table. added flash read access timing characteristics. in the ?adc conversion characteristics? table: ? deleted the entry for tuep (precision channels are not implemented on this device). ? changed the specification for inl (was min = ?1.5 lsb and max = 1.5 lsb, is min = max = 2.5 lsb). ? revised the entry for i inj (was 10 ma, is 5 ma). ? changed the max specifications for r sw1 (was 3 k ? , is 1 k ? ) and for r sw2 (was 2 k ? , is 1 k ? ). added the ?lcd driver electrical characteristics? section. revised the table titles in the ?pad ac specifications? section. added the ?quadspi timing? section. revised the ?jtag interface timing? table. revised the ?nexus debug port timing? table. renamed the ?interface to tft lcd panels?ac cess level? section (is ?interface to tft lcd panels?) and revised the table (title and contents) within it. in the ?dspi timing? table, added a min specification for t csc (is 20 ns). in the dspi section, added a note (referring to the ?dspi timing? table) to each timing diagram. revised the ?ordering information? section. table 66. document revision history revision date substantive changes
mpc5606s microcontroller data sheet, rev. 8 revision history freescale semiconductor 134 6 14 jan 2011 editorial changes and improvements. swapped xtal and extal pins for the 208-pin bga package and throughout. in the ?pinout and signal descriptions? se ction, changed warning labels to caution labels. updated the ?absolute maximum ratings? and ?recommended operating conditions? tables. added footnote reference to v ss12 in ?recommended operating conditions (3.3 v)? table. updated the ?connecting power supply pins? section. removed footnote regarding characterization in the ?thermal characteristics? table. updated the v dd12 /v ddpll operating voltages in the ?e lectromagnetic interference? table. added typical values and updated the ?voltage regulator electrical characteristics,? ?low-power voltage regulator electrical characteristics,? and ?ultra-low-power voltage regulator electrical characteristics? tables. updated classifications and values in the ?low voltage monitor electrical characteristics? table. made major modifications and updates to the ?dc electrical characteristics? table. made major modifications and updates to the ?i/o input dc electrical characteristics? table. made major modifications and updates to the ?i/o pull-up/pull-down dc electrical characteristics? table. changed ?smc? pads to ?smd? pads throughout. made updates to the ?smd pad elec trical characteristics? table. added run current during reset to the ?res et electrical characteristics? table. updated the fmpll jitter (peak to peak) specification in the ?fmpll electrical characteristics? table. updated f firc and t fircsu in the ?fast internal rc oscillator (16 mhz) electrical characteristics? table. updated f sirc and t sircsu in the ?slow internal rc oscillator (128 khz) electrical characteristics? table. removed ?symmetric? pad type from the ?pad ac specifications (5.0 v, pad3v5v = 0)? table. removed ?symmetric? pad type from the ?pad ac specifications (3.3 v, pad3v5v = 1)? table. updated v dd12 post-trimming minimum value in the ?low-power voltage regulator electrical characteristics? table. updated v dd12 post-trimming minimum va lue in the ?ultra-low-power voltage regulator electrical characteristics? table. updated v lv d lv c o r h maximum value in the ?low voltage monitor electrical characteristics? table. updated v lv d lv c o r l minimum value in the ?low voltage monitor electrical characteristics? table. updated value of v dd12 /v ddpll operating voltages in the ?input dc electrical characteristics? table. corrected erroneous value of i lkg (105c case) in the ?input dc electrical characteristics? table. table 66. document revision history revision date substantive changes
revision history mpc5606s microcontroller data sheet, rev. 8 freescale semiconductor 135 7 17 mar 2011 in the ?operating mode summary? table, updated the ?mode switch over? specification for ?halt? to be 200.69 s. changed ?advance information? to ?t echnical data? on the front page. inserted standalone note regarding ram data retention when v dd12 is not less than 1.08 v. added footnote to ?ssd electrical characte ristics? table that specifies vdd and tj. in the ?ssd electrical characteristics? table, changed the minimum value of i vref from 2.5 ma to 1.85 ma. updated the entire ?dspi timing? table. 8 10 oct 2011 changed usages of io to i/o throughout document. in voltage supply pins section, removed phr ase ?or noise free supply? from bullet item. in ?recommended operating conditions (3.3 v)? table, changed v ssr in footnote 2 to v ssr . in ?recommended operating conditions (5.0 v)? table, changed v ss12 in footnote 3 to v ssr . in ?allowed ballast components? table, added 2sd1000 component and specifications. in ?voltage regulator electrical characteristics? section, added figure ?voltage regulator capacitance connection.? added ?low voltage monitor vs. reset? figure to ?low voltage monitor electrical characteristics? section. added footnote ?lvdlvbkp has same post-trim thresholds as lvdlvcor? to ?low voltage monitor electrical characteristics? table. added ? sircpre and ? sirctrim specifications to ?slow internal rc oscillator (128 khz) electrical characteristics? table. added footnote to ?adc conversion charac teristics (continued)? table ?at 32 mhz the minimum sampling time must be at least 180 ns.? (ps1844) in quadspi section, reformatted quadspi out put timing diagram, quadspi input timing diagram, and quadspi clock profile figures. in figure ?start-up rese t requirements,? changed ?reset ? to ?v reset .? in ?low voltage monitor electrical characteristics,? table, changed v lv d lv c o r h max to 1.15v. in ?smd pad electrical characteristics? table, changed v omatch ?c? characteristic to c. in ?voltage regulator electrical characteristics? table, removed upper limit for post-trim v dd12 and raised min post-trim v dd12 voltage to 1.15 v. in ?low-power voltage regulator electrical c haracteristics? table, removed upper limit for post-trim v dd12 and raised min post-trim v dd12 voltage to 1.15 v. in ?ultra-low-power voltage regulator electrical characteristics? table, removed upper limit for post-trim v dd12 and raised min post-trim v dd12 voltage to 1.15 v. in ?ssd electrical characteristics? table, changed values for v vref from v ddm /2?0.02 and v ddm /2 + 0.02 to v ddm /2 ? 0.03 and v ddm /2 + 0.03 added ?voltage regulator capa citance connection? figure. reformatted ?debug pin descriptions? table (contents not changed). in ?16-channel emios module channel configuration? table, changed vreg startup for standby mode from 50 s to 250 s. table 66. document revision history revision date substantive changes
mpc5606s microcontroller data sheet, rev. 8 revision history freescale semiconductor 136 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com document number: mpc5606s rev. 8 11/2011 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freesc ale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2008?2011. all rights reserved.

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